Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop 1 Features 3 Description • AvailableintheTexasInstruments This single positive-edge-triggered D-type flip-flop is 1 designedfor1.65-Vto5.5-VV operation. NanoFree™Package CC • Supports5-VV Operation When data at the data (D) input meets the setup time CC requirement, the data is transferred to the Q output • InputsAcceptVoltagesto5.5V on the positive-going edge of the clock pulse. Clock • SupportsDownTranslationtoV CC triggering occurs at a voltage level and is not directly • Maximumt of4.2nsat3.3V related to the rise time of the clock pulse. Following pd the hold-time interval, data at the D input can be • LowPowerConsumption,10-µAMaximumI CC changedwithoutaffectingthelevelattheoutput. • ±24-mAOutputDriveat3.3V NanoFree™ package technology is a major • I SupportsLiveInsertion,Partial-Power-Down off breakthrough in IC packaging concepts, using the die Mode,andBack-DriveProtection asthepackage. • Latch-UpPerformanceExceeds100mAPer JESD78,ClassII This device is fully specified for partial-power-down applications using I . The I circuitry disables the • ESDProtectionExceedsJESD22 off off outputs, preventing damaging current backflow – 2000-VHuman-BodyModel(A114-A) throughthedevicewhenitispowereddown. – 200-VMachineModel(A115-A) DeviceInformation(1) – 1000-VCharged-DeviceModel(C101) PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications SN74LVC1G80DBV SOT-23(5) 2.90mm×1.60mm SN74LVC1G80DCK SC70(5) 2.00mm×1.25mm • TestandMeasurement SN74LVC1G80YZP DSBGA(5) 1.41mm×0.91mm • EnterpriseSwitching (1) For all available packages, see the orderable addendum at • TelecomInfrastructure theendofthedatasheet. • MotorDrives LogicDiagram(PositiveLogic) CLK 2 C C C 4 TG Q C C C C 1 D TG TG TG C C C (1) TG-TransmissionGate 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 DetailedDescription............................................ 11 2 Applications........................................................... 1 8.1 Overview.................................................................11 3 Description............................................................. 1 8.2 FunctionalBlockDiagram.......................................11 4 RevisionHistory..................................................... 2 8.3 FeatureDescription.................................................11 8.4 DeviceFunctionalModes........................................11 5 PinConfigurationandFunctions......................... 3 9 ApplicationandImplementation........................ 12 6 Specifications......................................................... 4 9.1 ApplicationInformation............................................12 6.1 AbsoluteMaximumRatings .....................................4 9.2 TypicalApplication .................................................12 6.2 ESDRatings..............................................................4 10 PowerSupplyRecommendations..................... 14 6.3 RecommendedOperatingConditions.......................4 6.4 ThermalInformation..................................................5 11 Layout................................................................... 14 6.5 ElectricalCharacteristics...........................................5 11.1 LayoutGuidelines.................................................14 6.6 TimingRequirements:T =–40°Cto+85°C............6 11.2 LayoutExample....................................................14 A 6.7 TimingRequirements:T =–40°Cto+125°C..........6 12 DeviceandDocumentationSupport................. 15 A 6.8 SwitchingCharacteristics:T =–40°Cto+85°C,C = 12.1 DocumentationSupport........................................15 A L 15pF..........................................................................7 12.2 ReceivingNotificationofDocumentationUpdates15 6.9 SwitchingCharacteristics:TA=–40°Cto+85°C,CL= 12.3 CommunityResources..........................................15 30pFor50pF...........................................................7 12.4 Trademarks...........................................................15 6.10 SwitchingCharacteristics:T =–40°Cto+125°C, A 12.5 ElectrostaticDischargeCaution............................15 C =30pFor50pF...................................................7 L 12.6 Glossary................................................................15 6.11 OperatingCharacteristics........................................7 13 Mechanical,Packaging,andOrderable 6.12 TypicalCharacteristics............................................8 Information........................................................... 15 7 ParameterMeasurementInformation..................9 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionR(December2013)toRevisionS Page • AddedApplicationssection,DeviceInformationtable,ESDRatingstable,ThermalInformationtable,Typical Characteristicssection,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • AddedmaxjunctiontemperaturetotheRecommendedOperatingConditionstable ........................................................... 5 • Addedoperatingfree-airtemperatureforYZPpackagetotheRecommendedOperatingConditionstable ........................5 • ChangedR valueforDBVpackagefrom:206°C/Wto:243.4°C/W................................................................................... 5 θJA • ChangedR valueforDCKpackagefrom:252°C/Wto:278.9°C/W................................................................................... 5 θJA • ChangedR valueforYZPpackagefrom:132°C/Wto:136.9°C/W.................................................................................... 5 θJA ChangesfromRevisionQ(January2007)toRevisionR Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 • UpdatedI inFeatures.......................................................................................................................................................... 1 off • Updatedoperatingtemperaturerange................................................................................................................................... 4 • AddedESDwarning ............................................................................................................................................................ 15 2 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 5 Pin Configuration and Functions YZPPackage 5-PinDSBGA DCKPackage BottomView 5-PinSC70 TopView GND 3 4 Q D 1 5 V CC CLK 2 CLK 2 D 1 5 VCC GND 3 4 Q DBVPackage 5-PinSOT-23 TopView D 1 5 V CC CLK 2 GND 3 4 Q PinFunctions(1) PIN I/O DESCRIPTION NO. NAME 1 D I Datainput 2 CLK I Clockinginput 3 GND — Groundpin 4 Q O Flip-flopoutput 5 V — Powerpin CC (1) SeeMechanical,Packaging,andOrderableInformationfordimensions Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltage(2) –0.5 6.5 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltageappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Junctiontemperature 150 °C J T Storagetemperature –65 150 ºC stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputclamp-currentratingsareobserved. (3) ThevalueofV isprovidedinRecommendedOperatingConditions. CC 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostatic Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) discharge Machinemodel(MM) ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent –16 mA OH V =3V CC –24 V =4.5V –32 CC (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeetheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs(SCBA004). 4 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 Recommended Operating Conditions (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseorfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 5 CC T Junctiontemperature 150 °C J DBVandDCKpackages –40 125 T Operatingfree-airtemperature °C A YZPpackage –40 85 6.4 Thermal Information SN74LVC1G80 THERMALMETRIC(1) DBV(SOT-23) DCK(SC70) YZP(DSBGA) UNIT 5PINS 5PINS 5PINS R Junction-to-ambientthermalresistance 243.4 278.9 136.9 °C/W θJA R Junction-to-case(top)thermalresistance 179 121.3 1.3 °C/W θJC(top) R Junction-to-boardthermalresistance 77.6 65.6 32.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 58.4 7.5 6.3 °C/W JT ψ Junction-to-boardcharacterizationparameter 77 64.9 32.6 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS VCC MIN TYP(1) MAX UNIT IOH=–100µA 1.65Vto5.5V VCC–0.1 IOH=–4mA 1.65V 1.2 IOH=–8mA 2.3V 1.9 VOH V IOH=–16mA 2.4 3V IOH=–24mA 2.3 IOH=–32mA 4.5V 3.8 IOL=100µA 1.65Vto5.5V 0.1 IOL=4mA 1.65V 0.45 IOL=8mA 2.3V 0.3 VOL V IOL=16mA 0.4 3V IOL=24mA 0.55 IOL=32mA 4.5V 0.55 II CLKorDinputs VI=5.5VorGND 0to5.5V ±10 µA Ioff VIorVO=5.5V 0 ±10 µA ICC VI=5.5VorGND, IO=0 1.65Vto5.5V 10 µA ΔICC OOntheerinipnuptuatstaVtCVCC–C0o.r6GVN,D 3Vto5.5V 500 µA Ci VI=VCCorGND T85A°=C–40°Cto 3.3V 3.5 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com 6.6 Timing Requirements: T = –40°C to +85°C A overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+85°C(unlessotherwisenoted)(seeFigure2) A VCC MIN MAX UNIT VCC=1.8V±0.15V VCC=2.5V±0.2V fclock Clockfrequency 160 MHz VCC=3.3V±0.3V VCC=5.5V±0.5V VCC=1.8V±0.15V VCC=2.5V±0.2V tw Pulseduration,CLKhighorlow 2.5 ns VCC=3.3V±0.3V VCC=5.5V±0.5V VCC=1.8V±0.15V 2.3 VCC=2.5V±0.2V 1.5 Datahigh VCC=3.3V±0.3V 1.3 VCC=5.5V±0.5V 1.1 tsu SetuptimebeforeCLK↑ ns VCC=1.8V±0.15V 2.5 VCC=2.5V±0.2V 1.5 Datalow VCC=3.3V±0.3V 1.3 VCC=5.5V±0.5V 1.1 VCC=1.8V±0.15V 0 VCC=2.5V±0.2V 0.2 th Holdtime,dataafterCLK↑ ns VCC=3.3V±0.3V 0.9 VCC=5.5V±0.5V 0.4 6.7 Timing Requirements: T = –40°C to +125°C A overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+125°C(unlessotherwisenoted)(seeFigure2) A VCC MIN MAX UNIT VCC=1.8V±0.15V VCC=2.5V±0.2V fclock Clockfrequency 160 MHz VCC=3.3V±0.3V VCC=5.5V±0.5V VCC=1.8V±0.15V VCC=2.5V±0.2V tw Pulseduration,CLKhighorlow 2.5 ns VCC=3.3V±0.3V VCC=5.5V±0.5V VCC=1.8V±0.15V 2.3 VCC=2.5V±0.2V 1.5 Datahigh VCC=3.3V±0.3V 1.3 VCC=5.5V±0.5V 1.1 tsu SetuptimebeforeCLK↑ ns VCC=1.8V±0.15V 2.5 VCC=2.5V±0.2V 1.5 Datalow VCC=3.3V±0.3V 1.3 VCC=5.5V±0.5V 1.1 VCC=1.8V±0.15V 0 VCC=2.5V±0.2V 0.2 th Holdtime,dataafterCLK↑ ns VCC=3.3V±0.3V 0.9 VCC=5.5V±0.5V 0.4 6 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 6.8 Switching Characteristics: T = –40°C to +85°C, C = 15 pF A L overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+85°C,C =15pF(unlessotherwisenoted)(see A L Figure2) FROM TO PARAMETER (INPUT) (OUTPUT) VCC MIN MAX UNIT VCC=1.8V±0.15V VCC=2.5V±0.2V fmax 160 MHz VCC=3.3V±0.3V VCC=5V±0.5V VCC=1.8V±0.15V 3 9.1 VCC=2.5V±0.2V 1.5 6 tpd CLK Q ns VCC=3.3V±0.3V 1.3 4.2 VCC=5V±0.5V 1.1 3.8 6.9 Switching Characteristics: T = –40°C to +85°C, C = 30 pF or 50 pF A L overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+85°C,C =30pFor50pF(unlessotherwisenoted) A L (seeFigure3) FROM TO PARAMETER (INPUT) (OUTPUT) VCC MIN MAX UNIT VCC=1.8V±0.15V VCC=2.5V±0.2V fmax 160 MHz VCC=3.3V±0.3V VCC=5V±0.5V VCC=1.8V±0.15V 4.4 9.9 VCC=2.5V±0.2V 2.3 7 tpd CLK Q ns VCC=3.3V±0.3V 2 5.2 VCC=5V±0.5V 1.3 4.5 6.10 Switching Characteristics: T = –40°C to +125°C, C = 30 pF or 50 pF A L overrecommendedoperatingfree-airtemperaturerange,T =–40°Cto+125°C,C =30pFor50pF(unlessotherwise A L noted)(seeFigure3) FROM TO PARAMETER (INPUT) (OUTPUT) VCC MIN MAX UNIT VCC=1.8V±0.15V VCC=2.5V±0.2V fmax 160 MHz VCC=3.3V±0.3V VCC=5V±0.5V VCC=1.8V±0.15V 4.4 12.5 VCC=2.5V±0.2V 2.3 8.5 tpd CLK Q ns VCC=3.3V±0.3V 2 6 VCC=5V±0.5V 1.3 5.5 6.11 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS VCC TYP UNIT VCC=1.8V 24 VCC=2.5V 24 Cpd Powerdissipationcapacitance f=10MHz pF VCC=3.3V 25 VCC=5V 27 Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com 6.12 Typical Characteristics ThisplotshowsthedifferentI valuesforvariousvoltagesonthedatainput(D).Voltagesweepontheinputisfrom0Vto7 CC V.V =5V. CC 12 11 10 9 8 A) 7 m (C 6 C 5 I 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VIN (V) D001 Figure1.I vsV CC IN 8 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 7 Parameter Measurement Information V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 15 pF 1 MW 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 15 pF 1 MW 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com Parameter Measurement Information (continued) V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 30 pF 1 kW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 30 pF 500W 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 50 pF 500W 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 50 pF 500W 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 8 Detailed Description 8.1 Overview The SN74LVC1G80 is a single positive-edge-trigger D-type flip-flop. Data at the input (D) is transferred to the output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows fordataattheinputtobechangedwithoutaffectingthelevelattheoutput,followingthehold-timeinterval. 8.2 Functional Block Diagram CLK 2 C C C 4 TG Q C C C C 1 D TG TG TG C C C Figure4. LogicDiagram(PositiveLogic) 8.3 Feature Description This device has a wide operating VCC range of 1.65 V to 5.5 V. The wide operating range allows for a broad range of systems the device can be used in. The output can handle This device is full specified for partial-power- down applications. When V = 0, the I circuitry disables the outputs, preventing damaging current backflow CC off throughthedevice. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSN74LVC1G80. Table1.FunctionTable INPUTS OUTPUT CLK D Q ↑ H L ↑ L H L X Q 0 Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information A useful application for the SN74LVC1G80 is using it as a frequency divider. By feeding back the output (Q) to the input (D), the output will toggle on every rising edge of the clock waveform. In other words, the output goes HIGH once every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two. The SN74LVC1G80 does not have preset or clear functions so the initial state of the output is unknown. This application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW. Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor theclockdivision. 9.2 Typical Application 10 k(cid:13) VCC GPIO Output 1 D 5 MCU SN74LVC1G80 CLK 2 CLK CLK/2 Q 4 3 Figure5. ClockFrequencyDivision 9.2.1 DesignRequirements For this application a resistor needs to be placed on the feedback line in order for the initialization voltage from the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be challengedbytheGPIOfromthemicrocontrollerandfromtheoutputoftheSN74LVC1G80. The SN74LVC1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus contentionbecauseitcandrivecurrentsthatwouldexceedmaximumlimits. 9.2.2 DetailedDesignProcedure 1. Recommendedinputconditions: – Forrisetimeandfalltimespecifications,see Δt/ΔvinRecommendedOperatingConditions. – Forspecifiedhighandlowlevels,seeV andV inRecommendedOperatingConditions. IH IL – Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any V . See CC RecommendedOperatingConditions. 2. Recommendedoutputconditions: – Loadcurrentsshouldnotexceed ±50mA.SeeAbsoluteMaximumRatings. – Output voltages are recommended to not go below 0 V and not exceed the V voltage. See CC RecommendedOperatingConditions. 12 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 Typical Application (continued) 3. Feedbackresistor: – A 10-kΩ resistor is chosen here to bias the input so the microcontroller GPIO output can initialize the input and output. The resistor value is important because a resistance too high, say at 1 MΩ, would cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause current to flow into the microcontroller,possiblydamagingthedevice. 9.2.3 ApplicationCurve Figure6. FrequencyDivision Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 SCES221S–APRIL1999–REVISEDNOVEMBER2016 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating listed in Absolute Maximum Ratings . Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-µF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-µF or 0.022-µF capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel.Thebypasscapacitormustbeinstalledasclosetothepowerterminalaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding corners.Onlythelastexample(BEST)maintainsconstanttracewidthandminimizesreflections. 11.2 Layout Example WORST BETTER BEST W 2 1W min. W Figure7. TraceExample 14 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G80

SN74LVC1G80 www.ti.com SCES221S–APRIL1999–REVISEDNOVEMBER2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs (SCBA004). 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks NanoFree,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN74LVC1G80

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC1G80DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C805, C80F, C80J, & no Sb/Br) C80R) SN74LVC1G80DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C80F & no Sb/Br) SN74LVC1G80DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C80F & no Sb/Br) SN74LVC1G80DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C805, C80F, C80J, & no Sb/Br) C80R) SN74LVC1G80DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C80F & no Sb/Br) SN74LVC1G80DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CX5, CXF, CXJ, CX & no Sb/Br) K, CXR) SN74LVC1G80DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CX5 & no Sb/Br) SN74LVC1G80DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CX5 & no Sb/Br) SN74LVC1G80DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CX5, CXF, CXJ, CX & no Sb/Br) K, CXR) SN74LVC1G80YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 (CX7, CXN) & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G80 : •Automotive: SN74LVC1G80-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1G80DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G80DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74LVC1G80DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G80DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G80DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G80DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G80YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G80DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G80DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G80DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G80DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G80YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE YZP0005 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP C SYMM 1 B D: Max = 1.418 mm, Min =1 .358 mm TYP 0.5 TYP E: Max = 0.918 mm, Min =0 .858 mm A 0.25 5X 1 2 0.21 0.015 C A B SYMM 4219492/A 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.23) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219492/A 05/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL SYMM TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219492/A 05/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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