Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear 1 Features 3 Description • AvailableintheTexasInstruments This single D-type flip-flop is designed for 1.65-V to 1 5.5-VV operation. NanoFree™Package CC • Supports5-VV Operation The SN74LVC1G175 device has an asynchronous CC clear (CLR) input. When CLR is high, data from the • InputsAcceptVoltagesto5.5V input pin (D) is transferred to the output pin (Q) on • SupportsDownTranslationtoV CC the clock's (CLK) rising edge. When CLR is low, Q is • Maxt of4.3nsat3.3V forced into the low state, regardless of the clock edge pd ordataonD. • LowPowerConsumption,10-µAMaxI CC • ±24-mAOutputDriveat3.3V NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die • I SupportsLiveInsertion,Partial-Power-Down off asthepackage. Mode,andBack-DriveProtection • Latch-UpPerformanceExceeds100mAPer This device is fully specified for partial-power-down JESD78,ClassII applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow • ESDProtectionExceedsJESD22 throughthedevicewhenitispowereddown. – 2000-VHuman-BodyModel(A114-A) – 200-VMachineModel(A115-A) DeviceInformation(1) – 1000-VCharged-DeviceModel(C101) PARTNUMBER PACKAGE BODYSIZE(NOM) SN74LVC1G175DBV SOT-23(6) 2.90mm×1.60mm 2 Applications SN74LVC1G175DCK SC70(6) 2.00mm×1.25mm • TV/SetTopBox/Audio SN74LVC1G175DRY SON(6) 1.45mm×1.00mm SN74LVC1G175YZP DSBGA(6) 1.41mm×0.91mm • EPOS(ElectronicPoint-of-Sale) • MotorDrives (1) For all available packages, see the orderable addendum at theendofthedatasheet. • PC/Notebook • Servers • FactoryAutomationandControl • Tablets • MedicalHealthcareandFitness • SmartGrid • TelecomInfrastructure • EnterpriseSwitching • Projectors • Storage LogicDiagram(PositiveLogic) 6 CLR 1 CLK 3 D D 4 C1 Q R 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8 DetailedDescription............................................ 10 2 Applications........................................................... 1 8.1 Overview.................................................................10 3 Description............................................................. 1 8.2 FunctionalBlockDiagram.......................................10 4 RevisionHistory..................................................... 2 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................10 5 PinConfigurationandFunctions......................... 3 9 ApplicationandImplementation........................ 11 6 Specifications......................................................... 4 9.1 ApplicationInformation............................................11 6.1 AbsoluteMaximumRatings .....................................4 9.2 TypicalApplication .................................................11 6.2 ESDRatings..............................................................4 10 PowerSupplyRecommendations..................... 12 6.3 RecommendedOperatingConditions......................4 6.4 ThermalInformation..................................................5 11 Layout................................................................... 12 6.5 ElectricalCharacteristics...........................................5 11.1 LayoutGuidelines.................................................12 6.6 TimingRequirements,–40°Cto85°C.......................6 11.2 LayoutExample....................................................13 6.7 TimingRequirements,–40°Cto125°C.....................6 12 DeviceandDocumentationSupport................. 14 6.8 SwitchingCharacteristics,–40°Cto85°C.................6 12.1 DocumentationSupport........................................14 6.9 SwitchingCharacteristics,–40°Cto85°C.................6 12.2 CommunityResources..........................................14 6.10 SwitchingCharacteristics,–40°Cto125°C.............7 12.3 Trademarks...........................................................14 6.11 OperatingCharacteristics........................................7 12.4 ElectrostaticDischargeCaution............................14 6.12 TypicalCharacteristics............................................7 12.5 Glossary................................................................14 7 ParameterMeasurementInformation..................8 13 Mechanical,Packaging,andOrderable Information........................................................... 14 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(December2013)toRevisionG Page • AddedApplications................................................................................................................................................................. 1 • AddedDeviceInformationtable............................................................................................................................................. 1 • AddedESDRatingsstable..................................................................................................................................................... 4 • AddedThermalInformationtable........................................................................................................................................... 5 • AddedTypicalCharacteristics................................................................................................................................................ 7 ChangesfromRevisionE(June2008)toRevisionF Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • DeletedOrderingInformationtable........................................................................................................................................ 1 • UpdatedFeatures................................................................................................................................................................... 1 2 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 5 Pin Configuration and Functions DBVPackage 6-PinSOT-23 DCKPackage TopView 6-PinSC70 TopView CLK 1 6 CLR CLK 1 6 CLR GND 2 5 V CC GND 2 5 V CC D 3 4 Q D 3 4 Q DRYPackage 6-PinSON YZPPackage TopView 6-PinDSBGA BottomView CLK 1 6 CLR D 3 4 Q GND 2 5 VCC GND 2 5 VCC D 3 4 Q CLK 1 6 CLR Seemechanicaldrawingsfordimensions. PinFunctions PIN I/O DESCRIPTION NAME NO. CLK 1 I ClockInput CLR 6 I ClearDataInput D 3 I DataInput GND 2 — Ground Q 4 O Output V 5 — Power CC Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltage –0.5 6.5 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltageappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 6.2 ESD Ratings VALUE UNIT Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V V (ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent –16 mA OH V =3V CC –24 V =4.5V –32 CC (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. 4 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 Recommended Operating Conditions (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseorfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 10 CC T Operatingfree-airtemperature –40 125 °C A 6.4 Thermal Information SN74LVC1G175 THERMALMETRIC(1) DBV(SOT-23) DCK(SC70) DRY(SON) YZP(DSBGA) UNIT 6PINS 6PINS 6PINS 6PINS R Junction-to-ambientthermalresistance 165 259 234 123 °C/W θJA (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) –40°Cto85°C –40°Cto125°C PARAMETER TESTCONDITIONS VCC MIN TYP(1) MAX MIN TYP(1) MAX UNIT IOH=–100µA 1.65Vto5.5V VCC –0.1 VCC –0.1 IOH=–4mA 1.65V 1.2 1.2 IOH=–8mA 2.3V 1.9 1.9 VOH V IOH=–16mA 2.4 2.4 3V IOH=–24mA 2.3 2.3 IOH=–32mA 4.5V 3.8 3.8 IOL=100µA 1.65Vto5.5V 0.1 0.1 IOL=4mA 1.65V 0.45 0.45 IOL=8mA 2.3V 0.3 0.3 VOL V IOL=16mA 0.4 0.4 3V IOL=24mA 0.55 0.55 IOL=32mA 4.5V 0.55 0.55 II VI=5.5VorGND 0to5.5V ±1 ±1 µA Ioff VIorVO=5.5V 0 ±10 ±10 µA ICC VI=5.5VorGND,IO=0 1.65Vto5.5V 10 10 µA ΔICC OOntheerinipnuptuatstaVtCVCCC–o0r.6GVN,D 3Vto5.5V 500 500 µA Ci VI=VCCorGND 3.3V 3 3 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 6.6 Timing Requirements, –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2) –40°Cto85°C VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX fclock Clockfrequency 100 125 150 175 MHz CLR Low 5.6 3 2.8 2.5 tw Pulseduration ns CLK Highorlow 3.5 3 2.8 2.5 Data 3 2.5 2 1.5 tsu Setuptime,beforeCLK↑ ns CLRinactive 0 0 0.5 0.5 th Holdtime,dataafterCLK↑ 0 0 0.5 0.5 ns 6.7 Timing Requirements, –40°C to 125°C overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure2) –40°Cto125°C VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX fclock Clockfrequency 100 125 150 175 MHz CLR Low 5.6 3 2.8 2.5 tw Pulseduration ns CLK Highorlow 3.5 3 2.8 2.5 Data 3 2.5 2 1.5 tsu Setuptime,beforeCLK↑ ns CLRinactive 0.5 0.5 0.7 0.7 th Holdtime,dataafterCLK↑ 0.5 0.5 0.7 0.7 ns 6.8 Switching Characteristics, –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure2) L –40°Cto85°C PARAMETER FROM TO VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX fmax 100 125 150 175 MHz CLK 2.5 12.9 2 6.5 1.4 4.6 1 3 tpd Q ns CLR 2.5 12.4 2 6 1.2 4.3 1 3.2 6.9 Switching Characteristics, –40°C to 85°C overrecommendedoperatingfree-airtemperaturerange,C =30pFor50pF(unlessotherwisenoted)(seeFigure3) L –40°Cto85°C PARAMETER FROM TO VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX fmax 100 125 150 175 MHz CLK 2.7 13.4 2.2 7.1 1.6 5.7 1.5 4 tpd Q ns CLR 2.7 12.9 2.2 7 1.5 5.8 1.3 4.1 6 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 6.10 Switching Characteristics, –40°C to 125°C overrecommendedoperatingfree-airtemperaturerange,C =30pFor50pF(unlessotherwisenoted)(seeFigure3) L –40°Cto125°C PARAMETER FROM TO VCC=1.8V VCC=2.5V VCC=3.3V VCC=5V UNIT (INPUT) (OUTPUT) ±0.15V ±0.2V ±0.3V ±0.5V MIN MAX MIN MAX MIN MAX MIN MAX fmax 100 125 150 175 MHz CLK 2.7 15.4 2.2 8.1 1.6 6.7 1.5 5 tpd Q ns CLR 2.7 14.9 2.2 8 1.5 6.8 1.3 5.1 6.11 Operating Characteristics T =25°C A V =1.8V V =2.5V V =3.3V V =5V CC CC CC CC PARAMETER TESTCONDITIONS UNIT TYP TYP TYP TYP C Powerdissipationcapacitance f=10MHz 18 19 19 21 pF pd 6.12 Typical Characteristics 21.5 21 pF) 20.5 e ( c n cita 20 a p a C n 19.5 o ati p si 19 s Di er ow18.5 P 18 Typical &KDUDFWHU« 17.5 0 1 2 3 4 5 6 Supply Voltage [V ] (V) CC C001 Figure1.VoltagevsCapacitance Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 7 Parameter Measurement Information V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 15 pF 1 MW 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 15 pF 1 MW 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 15 pF 1 MW 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 Parameter Measurement Information (continued) V LOAD R S1 Open From Output L TEST S1 Under Test GND t /t Open C PLH PHL (see NoteA)L RL tPLZ/tPZL VLOAD t /t GND PHZ PZH LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L D I r f 1.8 V±0.15 V V £2 ns V /2 2 ×V 30 pF 1 kW 0.15 V CC CC CC 2.5 V±0.2 V V £2 ns V /2 2 ×V 30 pF 500W 0.15 V CC CC CC 3.3 V±0.3 V 3 V £2.5 ns 1.5 V 6 V 50 pF 500W 0.3 V 5 V±0.5 V V £2.5 ns V /2 2 ×V 50 pF 500W 0.3 V CC CC CC V I Timing Input V M 0 V t W VI tsu th V Input V V I M M Data Input V V M M 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VM VM VI COounttpruotl VM VM VI 0 V 0 V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WSav1e afot rVm 1 VM V + V LOAD VOL (see NoteL OBAD) OL D VOL t t PHL PLH t t PZH PHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH–VD VOH VOL (see Note B) »0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W. O D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 8 Detailed Description 8.1 Overview ThissingleD-typeflip-flopisdesignedfor1.65-Vto5.5-VV operation. CC The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the lowstate,regardlessoftheclockedgeordataonD. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. 8.2 Functional Block Diagram 6 CLR 1 CLK 3 D D 4 C1 Q R 8.3 Feature Description The SN74LVC1G175 device has a wide operating V range of 1.65 V to 5.5 V, which allows it to be used in a CC broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when V =0. CC 8.4 Device Functional Modes Table1liststhefunctionalmodesforSN74LVC1G175. Table1.FunctionTable INPUTS OUTPUT CLR CLK D Q H ↑ L L H ↑ H H H HorL X Q 0 L X X L 10 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information Multiple SN74LVC1G175 devices can be used in tandem to create a shift register of arbitrary length. In this example, we use four SN74LVC1G175 devices to form a 4-bit serial shift register. By connecting all CLK inputs to a common clock pulse and tying each output of one device to the next, we can store and load 4-bit values on demand. We demonstrate loading the 4 bit value 1101 into memory by setting Serial Input Data to each desired memory bit, and by sending a clock pulse for each bit, we sequentially move all stored bits from left to right (A →B→C→D) 9.2 Typical Application VCC = 5 V Serial Serial Input Data D VCC Q D VCC Q D VCC Q D VCC Q Output Data SN74LVC1G175 SN74LVC1G175 SN74LVC1G175 SN74LVC1G175 A B C D Clock CLK GND CLK GND CLK GND CLK GND Pulse Figure4. 4-BitSerialShiftRegister Table2.StoredDataValues SerialInputData StoredA StoredB StoredC StoredD 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 9.2.1 DesignRequirements The SN74LVC1G175 device uses CMOS technology and has balanced output drive. Care must be taken to avoidbuscontentionbecauseitcandrivecurrentsthatwouldexceedmaximumlimits. The SN74LVC1G175 allows storing digital signals with a digital control signal. All input signals should remain as closeaspossibletoeither0VorV foroptimaloperation. CC 9.2.2 DetailedDesignProcedure 1. Recommendedinputconditions: – Forrisetimeandfalltimespecifications,see Δt/Δvinthetable. – Forspecifiedhighandlowlevels,seeV andV inthetable. IH IL – Inputsandoutputsareovervoltagetolerantandcanthereforegoashighas5.5VatanyvalidV . CC 2. Recommendedoutputconditions: – Loadcurrentsshouldnotexceed ±50mA. Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 3. Frequencyselectioncriterion: – TheeffectsoffrequencyupontheoutputcurrentshouldbestudiedinFigure5. – Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout practiceslistedintheLayoutsection. 9.2.3 ApplicationCurve 20.00 tpdfrom CLRtoQ. CL=30 pFor50 pF 15.00 –40°C to 125°C s) n ( pd10.00 x t a M 5.00 0.00 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 Voltage(V) C001 Figure5. MaxtpdvsVoltageofLVCFamily 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the table. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled V , then a 0.01-μF or 0.022-μF CC capacitor is recommended for each V because the V pins are tied together internally. For devices with dual CC CC supply pins operating at different voltages, for example V and V , a 0.1-µF bypass capacitor is recommended CC DD foreachsupplypin.Torejectdifferentfrequenciesofnoise,usemultiplebypasscapacitorsinparallel.Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close tothepowerterminalaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines Whenusingmultiple-bitlogicdevices,inputsmustneverfloat. In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected, because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float outputs, CC unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when disabled. 12 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 www.ti.com SCES560G–MARCH2004–REVISEDJUNE2015 11.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram Copyright©2004–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC1G175

SN74LVC1G175 SCES560G–MARCH2004–REVISEDJUNE2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • ImplicationsofSloworFloatingCMOSInputs,SCBA004 • SelectingtheRightTexasInstrumentsSignalSwitch,SZZA030 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks NanoFree,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 14 SubmitDocumentationFeedback Copyright©2004–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G175

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74LVC1G175DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R) & no Sb/Br) 74LVC1G175DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R) & no Sb/Br) 74LVC1G175DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 D65 & no Sb/Br) 74LVC1G175DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 D65 & no Sb/Br) SN74LVC1G175DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R) & no Sb/Br) SN74LVC1G175DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 (C755, C75R) & no Sb/Br) SN74LVC1G175DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (D65, D6J, D6R) & no Sb/Br) SN74LVC1G175DCKT ACTIVE SC70 DCK 6 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (D65, D6J, D6R) & no Sb/Br) SN74LVC1G175DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 D6 & no Sb/Br) SN74LVC1G175YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 D6N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G175 : •Enhanced Product: SN74LVC1G175-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74LVC1G175DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 74LVC1G175DCKTG4 SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G175DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G175DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G175DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G175DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G175DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G175DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74LVC1G175DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G175DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74LVC1G175DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G175DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G175DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 SN74LVC1G175YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74LVC1G175DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0 74LVC1G175DCKTG4 SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC1G175DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G175DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G175DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 SN74LVC1G175DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 SN74LVC1G175DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G175DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74LVC1G175DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G175DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74LVC1G175DCKT SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC1G175DCKT SC70 DCK 6 250 180.0 180.0 18.0 SN74LVC1G175DRYR SON DRY 6 5000 203.0 203.0 35.0 SN74LVC1G175YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE YZP0006 DSBGA - 0.5 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.5 MAX C SEATING PLANE 0.19 BALL TYP 0.05 C 0.15 0.5 TYP C SYMM 1 D: Max = 1.418 mm, Min =1 .358 mm B TYP 0.5 E: Max = 0.918 mm, Min =0 .858 mm TYP A 0.25 1 2 6X 0.21 SYMM 0.015 C A B 4219524/A 06/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFreeTM package configuration. www.ti.com

EXAMPLE BOARD LAYOUT YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.225) 1 2 A (0.5) TYP B SYMM C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.225) 0.05 MAX 0.05 MIN METAL METAL UNDER MASK SOLDER MASK ( 0.225) OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219524/A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com

EXAMPLE STENCIL DESIGN YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219524/A 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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