Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs 1 Features 2 Applications • MemberoftheTexasInstruments • Servers 1 Widebus™Family • PCsandNotebooks • OperatesFrom1.65Vto3.6V • NetworkSwitches • InputsAcceptVoltagesto5.5V • WearableHealthandFitnessDevices • Maxtpdof4.2nsat3.3V • TelecomInfrastructures • TypicalVOLP (OutputGroundBounce) • ElectronicPointsofSale <0.8VatV =3.3V,T =25°C CC A • TypicalV (OutputV Undershoot) 3 Description OHV OH >2VatV =3.3V,T =25°C The SN74LVC16373A device is a 16-bit transparent CC A • I SupportsLive-Insertion,Partial-Power-Down D-type latch which is designed for 1.65-V to 3.6-V off V operation. Mode,andBack-DriveProtection CC • SupportsMixed-ModeSignalOperation(5-VInput DeviceInformation(1) andOutputVoltagesWith3.3-VV ) CC PARTNUMBER PACKAGE BODYSIZE(NOM) • Latch-UpPerformanceExceeds100mAPer TSSOP(48) 12.50mm×6.10mm JESD78,ClassII TVSOP(48) 9.70mm×4.40mm • ESDProtectionExceedsJESD22 SSOP(48) 15.80mm×7.49mm – 2000-VHuman-BodyModel(A114-A) SN74LVC16373A BGAMICROSTAR 7.00mm×4.50mm – 1000-VCharged-DeviceModel(C101) JUNIOR(56) BGAMICROSTAR 8.00mm×5.50mm JUNIOR(54) (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic 1 24 1OE 2OE 48 25 1LE 2LE C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription............................................ 11 2 Applications........................................................... 1 9.1 Overview.................................................................11 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.......................................11 4 SimplifiedSchematic............................................. 1 9.3 FeatureDescription.................................................11 9.4 DeviceFunctionalModes........................................11 5 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 12 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................12 7 Specifications......................................................... 6 10.2 TypicalApplication ...............................................12 7.1 AbsoluteMaximumRatings .....................................6 11 PowerSupplyRecommendations..................... 13 7.2 HandlingRatings.......................................................6 12 Layout................................................................... 13 7.3 RecommendedOperatingConditions......................7 7.4 ThermalInformation..................................................7 12.1 LayoutGuidelines.................................................13 7.5 ElectricalCharacteristics...........................................8 12.2 LayoutExample....................................................13 7.6 TimingRequirements................................................8 13 DeviceandDocumentationSupport................. 14 7.7 SwitchingCharacteristics..........................................8 13.1 Trademarks...........................................................14 7.8 OperatingCharacteristics..........................................8 13.2 ElectrostaticDischargeCaution............................14 7.9 TypicalCharacteristics..............................................9 13.3 Glossary................................................................14 8 ParameterMeasurementInformation................10 14 Mechanical,Packaging,andOrderable Information........................................................... 14 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionA(September2005)toRevisionB Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 • AddedApplications................................................................................................................................................................. 1 • AddedDeviceInformationtable............................................................................................................................................. 1 • AddedHandlingRatingstable. .............................................................................................................................................. 6 • ChangedMAXambienttemperatureto125°C. ..................................................................................................................... 7 • AddedThermalInformationtable........................................................................................................................................... 7 • AddedTypicalCharacteristics. .............................................................................................................................................. 9 2 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 6 Pin Configuration and Functions DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 48 1LE 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 V 7 42 V CC CC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 V 18 31 V CC CC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2LE PinFunctions PIN I/O DESCRIPTION NO. NAME 1 OE I OutputEnable 2 1Q1 O 1Q1Output 3 1Q2 O 1Q2Output 4 GND — GroundPin 5 1Q3 O 1Q3Output 6 1Q4 O 1Q4Output 7 VCC — PowerPin 8 1Q5 O 1Q5Output 9 1Q6 O 1Q6Output 10 GND — GroundPin 11 1Q7 O 1Q7Output 12 1Q8 O 1Q8Output 13 2Q1 O 2Q1Output 14 2Q2 O 2Q2Output 15 GND — GroundPin 16 2Q3 O 2Q3Output 17 2Q4 O 2Q4Output 18 VCC — PowerPin 19 2Q5 O 2Q5Output 20 2Q6 O 2Q6Output Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com PinFunctions(continued) PIN I/O DESCRIPTION NO. NAME 21 GND — GroundPin 22 2Q7 O 2Q7Output 23 2Q8 O 2Q8Output 24 2OE O OutputEnable2 25 2LE I LatchEnable2 26 2D8 I 2D8Input 27 2D7 I 2D7Input 28 GND — GroundPin 29 2D6 I 2D6Input 30 2D5 I 2D5Input 31 VCC — PowerPin 32 2D4 I 2D4Input 33 2D3 I 2D3Input 34 GND — GroundPin 35 2D2 I 2D2Input 36 2D1 I 2D1Input 37 1D8 I 1D8Input 38 1D7 I 1D7Input 39 GND — GroundPin 40 1D6 I 1D6Input 41 1D5 I 1D5Input 42 VCC — PowerPin 43 1D4 I 1D4Input 44 1D3 I 1D3Input 45 GND — GroundPin 46 1D2 I 1D2Input 47 1D1 I 1D1Input 48 1LE I LatchEnable1 4 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K PinAssignments(1)(56-BallGQLorZQLPackage) 1 2 3 4 5 6 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 V V 1D3 1D4 CC CC D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 V V 2D6 2D5 CC CC J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2LE (1) NC–Nointernalconnection GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J PinAssignments(1)(54-BallGRDorZRDPackage) 1 2 3 4 5 6 A 1Q1 NC 1OE 1LE NC 1D1 B 1Q3 1Q2 NC NC 1D2 1D3 C 1Q5 1Q4 V V 1D4 1D5 CC CC D 1Q7 1Q6 GND GND 1D6 1D7 E 2Q1 1Q8 GND GND 1D8 2D1 F 2Q3 2Q2 GND GND 2D2 2D3 G 2Q5 2Q4 V V 2D4 2D5 CC CC H 2Q7 2Q6 NC NC 2D6 2D7 J 2Q8 NC 2OE 2LE NC 2D8 (1) NC–Nointernalconnection Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O V Voltagerangeappliedtoanyoutputinthehighorlowstate(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthrougheachV orGND ±100 mA CC (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintheRecommendedOperatingConditionstable. CC 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) 0 2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 CC V =1.65Vto1.95V 0.35×V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 CC V Inputvoltage 0 5.5 V I Highorlowstate 0 V CC V Outputvoltage V O High-impedancestate 0 5.5 V =1.65V –4 CC V =2.3V –8 CC I High-leveloutputcurrent mA OH V =2.7V –12 CC V =3V –24 CC V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent mA OL V =2.7V 12 CC V =3V 24 CC Δt/Δv Inputtransitionriseandfallrate 10 ns/V T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 7.4 Thermal Information DL THERMALMETRIC(1) UNIT 48PINS R Junction-to-ambientthermalresistance 68.4 θJA R Junction-to-case(top)thermalresistance 34.7 θJC(top) R Junction-to-boardthermalresistance 41.0 θJB °C/W ψ Junction-to-topcharacterizationparameter 12.3 JT ψ Junction-to-boardcharacterizationparameter 40.4 JB R Junction-to-case(bottom)thermalresistance n/a θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =–100μA 1.65Vto3.6V V –0.2 OH CC I =–4mA 1.65V 1.2 OH I =–8mA 2.3V 1.7 OH V V OH 2.7V 2.2 I =–12mA OH 3V 2.4 I =–24mA 3V 2.2 OH I =100μA 1.65Vto3.6V 0.2 OL I =4mA 1.65V 0.45 OL V I =8mA 2.3V 0.7 V OL OL I =12mA 2.7V 0.4 OL I =24mA 3V 0.55 OL I V =0to5.5V 3.6V ±5 μA I I I V orV =5.5V 0 ±10 μA off I O I V =0to5.5V 3.6V ±10 μA OZ O V =V orGND 20 I CC I I =0 3.6V μA CC 3.6V≤V ≤5.5V(2) O 20 I ΔI OneinputatV –0.6V,OtherinputsatV orGND 2.7Vto3.6V 500 μA CC CC CC C V =V orGND 3.3V 5 pF i I CC C V =V orGND 3.3V 6.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A (2) Thisappliesinthedisabledstateonly. 7.6 Timing Requirements overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) V =1.8V±0.15V V =2.5V±0.2V V =2.7V V =3.3V±0.3V CC CC CC CC UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 3.3 3.3 3.3 3.3 ns w t Setuptime,databeforeLE↓ 1.6 1.2 1.7 1.7 ns su t Holdtime,dataafterLE↓ 1 1.1 1.2 1.2 ns h 7.7 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C±C0.15V C±C0.2V VCC=2.7V C±C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX D 1.5 6.4 1 4.2 1 4.9 1.6 4.2 t Q ns pd LE 1.5 7.1 1 4.8 1 5.3 2.1 4.6 t OE Q 1.5 6.7 1 4.7 1 5.7 1.3 4.7 ns en t OE Q 1.5 8.4 1 5 1 6.3 2.5 5.9 ns dis 7.8 Operating Characteristics T =25°C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipationcapacitance Outputsenabled 32 35 39 C f=10MHz pF pd perlatch Outputsdisabled 4 4 6 8 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 7.9 Typical Characteristics 6 8 TPD in ns 7 5 6 4 5 s s n n D - 3 D - 4 P P T T 3 2 2 1 1 TPD in ns 0 0 -100 -50 0 50 100 150 0 0.5 1 1.5 2 2.5 3 3.5 Temperature (qC) D001 VCC - V D002 Figure1.SN74LVC16373A Figure2.SN74LVC16373ALEtoQTDP LEtoQAcrossTemperature3.3-VV V vsTPDat25°C CC CC Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com 8 Parameter Measurement Information VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 9 Detailed Description 9.1 Overview The SN74LVC16373A device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch- enable (LE) input high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched atthelevelssetupattheDinputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retainedornewdatacanbeenteredwhiletheoutputsareinthehigh-impedancestate.Inputscanbedrivenfrom either3.3-Vor5-Vdevices.Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed3.3-V/5-Vsystem environment. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. 9.2 Functional Block Diagram 1 24 1OE 2OE 48 25 1LE 2LE C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages. Figure4. LogicDiagram(PositiveLogic) 9.3 Feature Description • Wideoperatingvoltagerange – Operatesfrom1.65Vto3.6V • Allowsdownvoltagetranslation – Inputsacceptvoltagesto5.5V • I feature off – AllowsvoltagesontheinputsandoutputswhenV is0V CC 9.4 Device Functional Modes FunctionTable (EachLatch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com 10 Application and Implementation 10.1 Application Information The SN74LVC16373A device is a high drive CMOS device that can be used for a multitude of bus-interface type applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. The inputsare5.5VtolerantallowingittotranslatedowntoV . CC 10.2 Typical Application Regulated 3.6 V OE Vcc LE 1D 1Q uC System Logic uC or 8D 8Q LEDs System Logic GND Figure5. TypicalApplicationDiagram 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloads;therefore,routingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs:See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels:See(V andV )intheRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendOutputConditions – Loadcurrentsshouldnotexceed50mAperoutputand100mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC 12 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

SN74LVC16373A www.ti.com SCAS755B–DECEMBER2003–REVISEDJUNE2014 Typical Application (continued) 10.2.3 ApplicationCurves 3 ICC 1.8 V ICC 2.5 V 2.5 ICC 3.3 V Hz 2 M cy - 1.5 n e u q Fre 1 0.5 0 0 10 20 30 40 50 60 ICC - V D003 Figure6.I vsFrequency CC 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μf is recommended; if there are multiple V pins, then 0.01 μf or 0.022 μf is recommended for each CC power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldneverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V , whichever makes more sense or is more convenient. It is generally acceptable to float outputs, CC unlessthepartisatransceiver. 12.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure7. LayoutDiagram Copyright©2003–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC16373A

SN74LVC16373A SCAS755B–DECEMBER2003–REVISEDJUNE2014 www.ti.com 13 Device and Documentation Support 13.1 Trademarks WidebusisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 14 SubmitDocumentationFeedback Copyright©2003–2014,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC16373A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74LVC16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A & no Sb/Br) 74LVC16373ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LD373A & no Sb/Br) SN74LVC16373ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A & no Sb/Br) SN74LVC16373ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LD373A & no Sb/Br) SN74LVC16373ADL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A & no Sb/Br) SN74LVC16373ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A & no Sb/Br) SN74LVC16373ADLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A & no Sb/Br) SN74LVC16373AZQLR LIFEBUY BGA ZQL 56 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LD373A MICROSTAR & no Sb/Br) JUNIOR SN74LVC16373AZRDR LIFEBUY BGA ZRD 54 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 LD373A MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC16373A : •Enhanced Product: SN74LVC16373A-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74LVC16373ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74LVC16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74LVC16373AZQLR BGAMI ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CROSTA RJUNI OR SN74LVC16373AZRDR BGAMI ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVC16373ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74LVC16373ADLR SSOP DL 48 1000 367.0 367.0 55.0 SN74LVC16373AZQLR BGAMICROSTAR ZQL 56 1000 350.0 350.0 43.0 JUNIOR SN74LVC16373AZRDR BGAMICROSTAR ZRD 54 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OUTLINE ZQL0056A JRBGA - 1 mm max height SCALE 2.100 PLASTIC BALL GRID ARRAY 4.6 B A 4.4 BALL A1 CORNER 7.1 6.9 1 MAX C SEATING PLANE 0.35 0.15 TYP BALL TYP 0.1 C 3.25 TYP SYMM (0.625) TYP K J (0.575) TYP H G 5.85 F SYMM TYP E D C 0.45 56X NOTE 3 0.35 B 0.15 C B A 0.08 C A 0.65 TYP 1 2 3 4 5 6 BALL A1 CORNER 0.65 TYP 4219711/B 01/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. No metal in this area, indicates orientation. www.ti.com

EXAMPLE BOARD LAYOUT ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY (0.65) TYP 56X ( 0.33) 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK 0.05 MAX 0.05 MIN METAL UNDER OPENING SOLDER MASK EXPOSED METAL ( 0.33) ( 0.33) METAL EXPOSED METAL SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219711/B 01/2017 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com

EXAMPLE STENCIL DESIGN ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY 56X ( 0.33) (0.65) TYP 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4219711/B 01/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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