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SN74LVC10APWR产品简介:
ICGOO电子元器件商城为您提供SN74LVC10APWR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74LVC10APWR价格参考¥0.53-¥1.52。Texas InstrumentsSN74LVC10APWR封装/规格:逻辑 - 栅极和逆变器, NAND Gate IC 3 Channel 14-TSSOP。您可以下载SN74LVC10APWR参考资料、Datasheet数据手册功能说明书,资料中有SN74LVC10APWR 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC GATE NAND 3CH 3-INP 14-TSSOP逻辑门 Triple 3-Input |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,逻辑门,Texas Instruments SN74LVC10APWR74LVC |
数据手册 | |
产品型号 | SN74LVC10APWR |
不同V、最大CL时的最大传播延迟 | 4.7ns @ 3.3V,50pF |
产品 | NAND |
产品目录页面 | |
产品种类 | 逻辑门 |
传播延迟时间 | 4.9 ns |
低电平输出电流 | 24 mA |
供应商器件封装 | 14-TSSOP |
其它名称 | 296-8445-6 |
包装 | Digi-Reel® |
单位重量 | 57.200 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | 14-TSSOP(0.173",4.40mm 宽) |
封装/箱体 | TSSOP-14 |
工作温度 | -40°C ~ 125°C |
工作温度范围 | - 40 C to + 125 C |
工厂包装数量 | 2000 |
最大工作温度 | + 125 C |
最小工作温度 | - 40 C |
栅极数量 | 3 Gate |
标准包装 | 1 |
特性 | - |
电压-电源 | 1.65 V ~ 3.6 V |
电流-输出高,低 | 24mA,24mA |
电流-静态(最大值) | 1µA |
电源电压-最大 | 3.6 V |
电源电压-最小 | 2 V |
电路数 | 3 |
系列 | SN74LVC10A |
输入/输出线数量 | 3 / 1 |
输入数 | 3 |
输入线路数量 | 3 |
输出线路数量 | 1 |
逻辑电平-低 | 0.7 V ~ 0.8 V |
逻辑电平-高 | 1.7 V ~ 2 V |
逻辑类型 | 与非门 |
逻辑系列 | LVC |
高电平输出电流 | - 24 mA |
SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O–JANUARY1993–REVISEDJULY2005 FEATURES D, DB, NS, OR PW PACKAGE • OperatesFrom1.65Vto3.6V (TOP VIEW) • SpecifiedFrom–40(cid:176) Cto85(cid:176) Cand –40(cid:176) Cto125(cid:176) C 1A 1 14 V CC • InputsAcceptVoltagesto5.5V 1B 2 13 1C • Maxt of4.9nsat3.3V 2A 3 12 1Y pd 2B 4 11 3C • TypicalV (OutputGroundBounce) OLP 2C 5 10 3B <0.8VatV =3.3V,T =25(cid:176) C CC A 2Y 6 9 3A • TypicalV (OutputV Undershoot) OHV OH GND 7 8 3Y >2VatV =3.3V,T =25(cid:176) C CC A • Latch-UpPerformanceExceeds250mAPer JESD17 RGY PACKAGE • ESDProtectionExceedsJESD22 (TOP VIEW) C – 2000-VHuman-BodyModel(A114-A) A C 1 V – 200-VMachineModel(A115-A) 1 14 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A 7 8 D Y N 3 G DESCRIPTION/ORDERING INFORMATION Thistriple3-inputpositive-NANDgateisdesignedfor1.65-Vto3.6-VV operation. CC TheSN74LVC10AperformstheBooleanfunctionY=A•B•CorY=A+B+Cinpositivelogic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators inamixed3.3-V/5-Vsystemenvironment. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A –40(cid:176) Cto85(cid:176) C QFN–RGY Reelof1000 SN74LVC10ARGYR LC10A Tubeof50 SN74LVC10AD SOIC–D Reelof2500 SN74LVC10ADR LVC10A Reelof250 SN74LVC10ADT SOP–NS Reelof2000 SN74LVC10ANSR LVC10A –40(cid:176) Cto125(cid:176) C SSOP–DB Reelof2000 SN74LVC10ADBR LC10A Tubeof90 SN74LVC10APW TSSOP–PW Reelof2000 SN74LVC10APWR LC10A Reelof250 SN74LVC10APWT (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1993–2005,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.
SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O–JANUARY1993–REVISEDJULY2005 FUNCTIONTABLE (EACHGATE) INPUTS OUTPUT A B C Y H H H L L X X H X L X H X X L H LOGICDIAGRAM,EACHGATE(POSITIVELOGIC) A B Y C Absolute Maximum Ratings (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6.5 V CC V Inputvoltagerange(2) –0.5 6.5 V I V Outputvoltagerange(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent – 50 mA O ContinuouscurrentthroughV orGND – 100 mA CC Dpackage (4) 86 DBpackage(4) 96 q Packagethermalimpedance NSpackage(4) 76 (cid:176) C/W JA PWpackage(4) 113 RGYpackage(5) 47 T Storagetemperaturerange –65 150 (cid:176) C stg P Powerdissipation T =–40(cid:176) Cto125(cid:176) C(6)(7) 500 mW tot A (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThevalueofV isprovidedintherecommendedoperatingconditionstable. CC (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (5) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. (6) FortheDpackage:above70(cid:176) C,thevalueofP derateslinearlywith8mW/K. tot (7) FortheDB,NS,andPWpackages:above60(cid:176) C,thevalueofP derateslinearlywith5.5mW/K. tot 2
SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O–JANUARY1993–REVISEDJULY2005 Recommended Operating Conditions(1) T =25(cid:176) C –40TO85(cid:176) C –40TO125(cid:176) C A UNIT MIN MAX MIN MAX MIN MAX Operating 1.65 3.6 1.65 3.6 1.65 3.6 V Supplyvoltage V CC Dataretentiononly 1.5 1.5 1.5 V =1.65Vto1.95V 0.65· V 0.65· V 0.65· V CC CC CC CC High-levelinput V V =2.3Vto2.7V 1.7 1.7 1.7 V IH voltage CC V =2.7Vto3.6V 2 2 2 CC V =1.65Vto1.95V 0.35· V 0.35· V 0.35· V CC CC CC CC Low-levelinput V V =2.3Vto2.7V 0.7 0.7 0.7 V IL voltage CC V =2.7Vto3.6V 0.8 0.8 0.8 CC V Inputvoltage 0 5.5 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V 0 V V O CC CC CC V =1.65V –4 –4 –4 CC High-level VCC=2.3V –8 –8 –8 I mA OH outputcurrent V =2.7V –12 –12 –12 CC V =3V –24 –24 –24 CC V =1.65V 4 4 4 CC Low-leveloutput VCC=2.3V 8 8 8 I mA OL current V =2.7V 12 12 12 CC V =3V 24 24 24 CC (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PAR- TA=25(cid:176) C –40TO85(cid:176) C –40TO125(cid:176) C TESTCONDITIONS V UNIT AMETER CC MIN TYP MAX MIN MAX MIN MAX I =–100m A 1.65Vto3.6V V –0.2 V –0.2 V –0.3 OH CC CC CC I =–4mA 1.65V 1.29 1.2 1.05 OH I =–8mA 2.3V 1.9 1.7 1.55 OH V V OH 2.7V 2.2 2.2 2.05 I =–12mA OH 3V 2.4 2.4 2.25 I =–24mA 3V 2.3 2.2 2 OH I =100m A 1.65Vto3.6V 0.1 0.2 0.3 OL I =4mA 1.65V 0.24 0.45 0.6 OL V I =8mA 2.3V 0.3 0.7 0.75 V OL OL I =12mA 2.7V 0.4 0.4 0.6 OL I =24mA 3V 0.55 0.55 0.8 OL I V =5.5VorGND 3.6V – 1 – 5 – 20 m A I I I V =V orGND, I =0 3.6V 1 10 40 m A CC I CC O OneinputatV –0.6V, CC D I OtherinputsatV or 2.7Vto3.6V 500 500 5000 m A CC CC GND C V =V orGND 3.3V 5 pF i I CC 3
SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O–JANUARY1993–REVISEDJULY2005 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) FROM TO TA=25(cid:176) C –40TO85(cid:176) C –40TO125(cid:176) C PARAMETER V UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX MIN MAX 1.8V– 0.15V 1 4.2 10.1 1 10.6 1 12.1 2.5V– 0.2V 1 2.9 7.3 1 7.8 1 9.9 t A,B,orC Y ns pd 2.7V 1 3.1 5.6 1 5.8 1 7.4 3.3V– 0.3V 1 2.7 4.7 1 4.9 1 6 t 3.3V– 0.3V 1 1.5 ns sk(o) Operating Characteristics T =25(cid:176) C A TEST PARAMETER V TYP UNIT CONDITIONS CC 1.8V 9 C Powerdissipationcapacitancepergate f=10MHz 2.5V 10 pF pd 3.3V 11 4
SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O–JANUARY1993–REVISEDJULY2005 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tPLH/tPHL Open (see Note CAL) RL tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VI tr/tf VM VLOAD CL RL VD 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V VI Timing Input VM 0 V tw VI tsu th VI Input VM VM Data Input VM VM 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI Output Input VM VM Control VM VM 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VLOAD/2 Output VM VM VOL (Ss1e ea tN VoLteO ABD) VM VOL + VD VOL tPHL tPLH tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH - VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms 5
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC10AD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC10A & no Sb/Br) SN74LVC10ADBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10ADG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC10A & no Sb/Br) SN74LVC10ADR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC10A & no Sb/Br) SN74LVC10ADT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC10A & no Sb/Br) SN74LVC10ANSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LVC10A & no Sb/Br) SN74LVC10APW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10APWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10APWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LC10A & no Sb/Br) SN74LVC10ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LC10A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC10ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC10ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC10ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LVC10APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC10APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC10ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC10ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC10ADT SOIC D 14 250 210.0 185.0 35.0 SN74LVC10ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC10APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC10APWT TSSOP PW 14 250 367.0 367.0 35.0 SN74LVC10ARGYR VQFN RGY 14 3000 367.0 367.0 35.0 PackMaterials-Page2
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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