Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops 1 Features 3 Description • 2-Vto5.5-VV Operation These dual positive-edge-triggered D-type flip-flops 1 CC aredesignedfor2-Vto5.5-VV operation. • Maximumt of8.5nsat5V CC pd • TypicalVOLP (OutputGroundBounce) DeviceInformation(1) <0.8VatV =3.3V,T =25°C CC A PARTNUMBER PACKAGE BODYSIZE(NOM) • TypicalV (OutputV Undershoot) OHV OH VQFN(14) 3.50mm×3.50mm >2.3VatV =3.3V,T =25°C CC A SOIC(14) 8.65mm×3.91mm • SupportMixed-ModeVoltageOperationon SN74LV74A SOP(14) 10.30mm×5.30mm AllPorts SSOP(14) 6.20mm×5.30mm • I SupportsPartial-Power-Down off TSSOP(14) 5.00mm×4.40mm ModeOperation (1) For all available packages, see the orderable addendum at • Latch-upPerformanceExceeds250mA theendofthedatasheet. PerJESD17 LogicDiagram,EachFlip-Flop • ESDProtectionExceedsJESD22 (PositiveLogic) – 2000-VHuman-BodyModel(A114-A) PRE – 500-VCharged-DeviceModel(C101) CLK C C C 2 Applications TG Q • ProgrammableLogicController(PLC) C C C C • DCSandPAC:AnalogInputModule D TG TG TG • AVReceiver Q C C C • ServerPSU CLR • STB,DVR,andStreamingMedia(Withdraw) • ServerMotherboard 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.UNLESSOTHERWISENOTED,thisdocumentcontainsPRODUCTION DATA.

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7 ParameterMeasurementInformation..................9 2 Applications........................................................... 1 8 DetailedDescription............................................ 10 3 Description............................................................. 1 8.1 Overview.................................................................10 4 RevisionHistory..................................................... 2 8.2 FunctionalBlockDiagram.......................................10 5 PinConfigurationandFunctions......................... 3 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................11 6 Specifications......................................................... 4 9 ApplicationandImplementation........................ 12 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 9.1 ApplicationInformation............................................12 6.3 RecommendedOperatingConditions.......................5 9.2 TypicalApplication .................................................12 6.4 ElectricalCharacteristics...........................................5 10 PowerSupplyRecommendations..................... 14 6.5 SwitchingCharacteristics:V =2.5V±0.2V........6 11 Layout................................................................... 14 CC 6.6 SwitchingCharacteristics:V =3.3V±0.3V........6 11.1 LayoutGuidelines.................................................14 CC 6.7 SwitchingCharacteristics:V =5V±0.5V...........6 11.2 LayoutExample....................................................14 CC 6.8 TimingRequirements:V =2.5V±0.2V..............6 12 DeviceandDocumentationSupport................. 15 CC 6.9 TimingRequirements:V =3.3V±0.3V..............7 12.1 DocumentationSupport........................................15 CC 6.10 TimingRequirements:V =5V±0.5V...............7 12.2 Trademarks...........................................................15 CC 6.11 NoiseCharacteristics..............................................7 12.3 ElectrostaticDischargeCaution............................15 6.12 OperatingCharacteristics........................................7 12.4 Glossary................................................................15 6.13 TypicalCharacteristics............................................8 13 Mechanical,Packaging,andOrderable Information........................................................... 15 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionL(April2005)toRevisionM Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 • RemovedOrderingInformationtable..................................................................................................................................... 1 2 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 5 Pin Configuration and Functions D,DGV,NS,orPWPackage 14-PINSOIC,SOP,SSOP,orTSSOP TopView 1CLR 1 14 VCC 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 2PRE 1Q 6 9 2Q GND 7 8 2Q RGYPackage 14-PINVQFN TopView R L C C C 1 V 1 14 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 2PRE 1Q 6 9 2Q 7 8 D Q N 2 G PinFunctions PIN I/O DESCRIPTION NO. NAME 1 1CLR I 1clear 2 1D I 1Dinput 3 1CLK I 1clock 4 1PRE I 1preset 5 1Q O 1Qoutput 6 1Q O 1Qoutput 7 GND – GND 8 2Q O 2Qoutput 9 2Q O 2Qoutput 10 2PRE I 2preset 11 2CLK I 2clock 12 2D I 2Dinput 13 2CLR I 2clear 14 Vcc – Supplyvoltageinput Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC V Inputvoltage(2) –0.5 7 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V O V Outputvoltage(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±50 mA CC Dpackage(4) 86 DBpackage(4) 96 DGVpackage(4) 127 θ Packagethermalimpedance °C/W JA NSpackage(4) 76 PWpackage(4) 113 RGYpackage(5) 47 T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto5.5Vmaximum. (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (5) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- 500 V C101(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) SN54LV74A(2) SN74LV74A UNIT MIN MAX MIN MAX V Supplyvoltage 2 5.5 2 5.5 V CC V =2V 1.5 CC V =2.3Vto2.7V V ×0.7 V ×0.7 CC CC CC V High-levelinputvoltage V IH V =3Vto3.6V V ×0.7 V ×0.7 CC CC CC V =4.5Vto5.5V V ×0.7 V ×0.7 CC CC CC V =2V 0.5 0.5 CC V =2.3Vto2.7V V ×0.3 V ×0.3 CC CC CC V Low-levelinputvoltage V IL V =3Vto3.6V V ×0.3 V ×0.3 CC CC CC V =4.5Vto5.5V V ×0.3 V ×0.3 CC CC CC V Inputvoltage 0 5.5 0 5.5 V I V Outputvoltage 0 V 0 V V O CC CC V =2V –50 –50 µA CC V =2.3Vto2.7V –2 –2 CC I High-leveloutputcurrent OH V =3Vto3.6V –6 –6 mA CC V =4.5Vto5.5V –12 –12 CC V =2V 50 50 µA CC V =2.3Vto2.7V 2 2 CC I Low-leveloutputcurrent OL V =3Vto3.6V 6 6 mA CC V =4.5Vto5.5V 12 12 CC V =2.3Vto2.7V 200 200 CC Δt/Δv Inputtransitionriseorfallrate V =3Vto3.6V 100 100 ns/V CC V =4.5Vto5.5V 20 20 CC T Operatingfree-airtemperature –55 125 –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. (2) ProductPreview 6.4 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LV74A(1) SN74LV74A SN74LV74A PARAMETER TESTCONDITIONS VCC –40°Cto85°C –40°Cto125°C UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX IOH=–50µA 2Vto5.5V VCC–0.1 VCC–01. VCC–0.1 VOH IOH=–2mA 2.3V 2 2 2 V IOH=–6mA 3V 2.48 2.48 2.48 IOH=–12mA 4.5V 3.8 3.8 3.8 IOL=50µA 2Vto5.5V 0.1 0.1 0.1 IOL=2mA 2.3V 0.4 0.4 0.4 VOL V IOL=6mA 3V 0.44 0.44 0.44 IOL=12mA 4.5V 0.55 0.55 0.55 II VI=5.5VorGND 0to5.5V ±1 ±1 ±1 µA ICC VI=VCCorGND, IO=0 5.5V 20 20 20 µA Ioff VIorVO=5.5V 0 5 5 5 µA 3.3V 2 2 2 Ci VI=VCCorGND pF 5V 2 2 2 (1) ProductPreview Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 6.5 Switching Characteristics: V = 2.5 V ± 0.2 V CC overrecommendedoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted)(seeFigure3) CC PARAMETER FROM TO LOAD TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX CL=15pF 50(2) 100(2) 40(2) 40 40 fmax MHz CL=50pF 30 70 25 25 25 PREorCLR 9.8(2) 14.8(2) 1(2) 17(2) 1 17 1 18 tpd CLK QorQ CL=15pF 11.1(2) 16.4(2) 1(2) 19(2) 1 19 1 20 ns PREorCLR 13 17.4 1 20 1 20 1 21 tpd QorQ CL=50pF ns CLK 14.2 20 1 23 1 23 1 24 (1) ProductPreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6.6 Switching Characteristics: V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure3) CC PARAMETER FROM TO LOAD TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX CL=15pF 80(2) 140(2) 70(2) 70 70 fmax MHz CL=50pF 50 90 45 45 45 PREorCLR 6.9(2) 12.3(2) 1(2) 14.5(2) 1 14.5 1 15.5 tpd CLK QorQ CL=15pF 7.9(2) 11.9(2) 1(2) 14(2) 1 14 1 15 ns PREorCLR 9.2 15.8 1 18 1 18 1 19 tpd QorQ CL=50pF ns CLK 10.2 15.4 1 17.5 1 17.5 1 18.5 (1) ProductPreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6.7 Switching Characteristics: V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure3) CC PARAMETER FROM TO LOAD TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX CL=15pF 130(2) 180(2) 110(2) 110 110 fmax MHz CL=50pF 90 140 75 75 75 PREorCLR 5(2) 7.7(2) 1(2) 9(2) 1 9 1 10 tpd CLK QorQ CL=15pF 5.6(2) 7.3(2) 1(2) 8.5(2) 1 8.5 1 9.5 ns PREorCLR 6.6 9.7 1 11 1 11 1 12 tpd QorQ CL=50pF ns CLK 7.2 9.3 1 10.5 1 10.5 1 11.5 (1) ProductPreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6.8 Timing Requirements: V = 2.5 V ± 0.2 V CC overrecommendedoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted)(seeFigure3) CC TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX PREorCLRlow 8 9 9 9 tw Pulseduration ns CLK 8 9 9 9 Data 8 9 9 9 tsu SetuptimebeforeCLK↑ ns PREorCLRinactive 7 7 7 7 th Holdtime,dataafterCLK↑ 0.5 0.5 0.5 0.5 ns (1) ProductPreview 6 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 6.9 Timing Requirements: V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure3) CC TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX PREorCLRlow 6 7 7 7 tw Pulseduration ns CLK 6 7 7 7 Data 6 7 7 7 tsu SetuptimebeforeCLK↑ ns PREorCLRinactive 5 5 5 5 th Holdtime,dataafterCLK↑ 0.5 0.5 0.5 0.5 ns (1) ProductPreview 6.10 Timing Requirements: V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure3) CC TA=25°C SN54LV74A(1) –S40N°7C4LtoV7845A°C –4S0N°C74tLoV17245A°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX PREorCLRlow 5 5 5 5 tw Pulseduration ns CLK 5 5 5 5 Data 5 5 5 5 tsu SetuptimebeforeCLK↑ ns PREorCLRinactive 3 3 3 3 th Holdtime,dataafterCLK↑ 0.5 0.5 0.5 0.5 ns (1) ProductPreview 6.11 Noise Characteristics(1) V =3.3V,C =50pF,T =25°C CC L A SN74LV74A PARAMETER UNIT MIN TYP MAX V Quietoutput,maximumdynamicV 0.1 0.8 V OL(P) OL V Quietoutput,minimumdynamicV 0 –0.8 V OL(V) OL V Quietoutput,minimumdynamicV 3.2 V OH(V) OH V High-leveldynamicinputvoltage 2.31 V IH(D) V Low-leveldynamicinputvoltage 0.99 V IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 6.12 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 3.3V 21 C Powerdissipationcapacitance C =50pF f=10MHz pF pd L 5V 23 Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 6.13 Typical Characteristics 8 12 7 10 6 8 5 s) s) n n D ( 4 D ( 6 P P T T 3 4 2 2 1 0 0 -100 -50 0 50 100 150 0 1 2 3 4 5 6 Temperature VCC D001 D002 Figure1.TPDvs.Temperatureat3.3V Figure2.TPDvs.VCCat25°C 8 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 7 Parameter Measurement Information VCC From Output Test From Output RL= 1 kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see NoteA) (see NoteA) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATEAND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VCC Output VCC Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC InO-Puhtapsuet 50%VCC 50% VCVCOL WaSv1e faot rVmC C1 50% VCC VOL+0.3V VOL (see Note B) tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH−0.3VV≈0O HV VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. CLincludes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics: PRR≤1 MHz, ZO= 50Ω, tr≤3ns,tf≤3 ns. D. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. E. tPLZandtPHZarethesameastdis. F. tPZLandtPZHarethesameasten. G. tPHLandtPLHare the same as tpd. H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 8 Detailed Description 8.1 Overview Thesedualpositive-edge-triggeredD-typeflip-flopsaredesignedfor2-Vto5.5-VV operation. CC A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The state of the output upon power-up is not known until the first valid clock edge has occurred while V is within Recommended Operating CC Conditions. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs,preventingdamagingcurrentbackflowthroughthedeviceswhentheyarepowereddown. 8.2 Functional Block Diagram PRE CLK C C C Q TG C C C C D TG TG TG Q C C C CLR Figure4. LogicDiagram,EachFlip-Flop(PositiveLogic) 8.3 Feature Description The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce stabilizestheperformanceofnon-switchingoutputswhileanotheroutputisswitching. 10 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 8.4 Device Functional Modes Table1.FunctionTable INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q Q 0 0 (1) Thisconfigurationisnonstable;thatis,itdoesnotpersistwhenPRE orCLRreturnstoitsinactive(high)level. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LV74A is a Low drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on theoutputs.Theinputscanacceptvoltagesto5.5VatanyvalidV makingitIdealfordowntranslation. CC 9.2 Typical Application Figure5. TypicalApplicationSchematic 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads soconsiderroutingandloadconditionstopreventringing. 12 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 Typical Application (continued) 9.2.2 DetailedDesignProcedure • Recommendedinputconditions: – SpecifiedHighandlowlevels.See(V andV )inRecommendedOperatingConditions. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC • Recommendedoutputconditions: – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – OutputsshouldnotbepulledaboveV . CC 9.2.3 ApplicationCurves Figure6. SwitchingCharacteristicsComparison Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 SN74LV74A

SN54LV74A,SN74LV74A SCLS381M–AUGUST1997–REVISEDMARCH2015 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the RecommendedOperatingConditions. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, TI recommends a 0.1-μF capacitor and if there are multiple V terminals then TI recommends a 0.01-μF CC or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor shouldbeinstalledascloseaspossibletothepowerterminalforbestresults. 11 Layout 11.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldnoteverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more convenient. Floating outputs is generally CC acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float whendisabled. 11.2 Layout Example Figure7. LayoutRecommendation 14 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated SN74LV74A

SN54LV74A,SN74LV74A www.ti.com SCLS381M–AUGUST1997–REVISEDMARCH2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: ImplicationsofSloworFloatingCMOSInputs,SCBA004 12.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 SN74LV74A

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV74AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 74LV74A & no Sb/Br) SN74LV74APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A & no Sb/Br) SN74LV74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LV74A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LV74A : •Automotive: SN74LV74A-Q1 •Enhanced Product: SN74LV74A-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV74ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV74ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV74ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV74ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV74APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV74APWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74LV74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV74APWT TSSOP PW 14 250 367.0 367.0 35.0 SN74LV74ARGYR VQFN RGY 14 3000 367.0 367.0 35.0 PackMaterials-Page2

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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