Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 SN74LV244A Octal Buffers and Drivers With 3-State Outputs 1 Features 2 Applications • 2-Vto5.5-VV Operation • ServersandNetworkSwitches 1 CC • Maxt of6.5nsat5V • LEDDisplays pd • TypicalV (OutputGroundBounce) • TelecomInfrastructure OLP <0.8VatV =3.3V,T =25°C • Motor-DriveControlBoards CC A • TypicalV (OutputV Undershoot) OHV OH 3 Description >2.3VatV =3.3V,T =25°C CC A The SN74LV244A octal buffers and line drivers are • SupportMixed-ModeVoltageOperationonAll designedfor2-Vto5.5-VV operation. Ports CC • I SupportsPartial-Power-DownModeOperation The SN74LV244A devices are designed specifically off to improve both performance and density of the 3- • Latch-UpPerformanceExceeds250-mAPer state memory address drivers, clock drivers, and bus- JESD17 oriented receivers and transmitters. These devices • ESDProtectionExceedsJESD22 are organized as two 4-bit line drivers with separate – 2000-VHuman-BodyModel(A114-A) output-enable(OE)inputs. – 200-VMachineModel(A115-A) DeviceInformation – 1000-VCharged-DeviceModel(C101) PARTNUMBER PACKAGE(PIN) BODYSIZE SN74LV244ADGV TVSOP(20) 5.00mm×4.40mm SN74LV244ADW SOIC(20) 12.80mm×7.50mm SN74LV244ANS SOP(20) 12.60mm×5.30mm SN74LV244APW TSSOP(20) 6.50mm×4.40mm SN74LV244ARGY VQFN(20) 4.50mm×3.50mm LogicDiagram(PositiveLogic) 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................10 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................10 3 Description............................................................. 1 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................10 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 11 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation............................................11 6 Specifications......................................................... 4 9.2 TypicalApplication .................................................11 6.1 AbsoluteMaximumRatings .....................................4 10 PowerSupplyRecommendations..................... 13 6.2 ESDRatings..............................................................4 11 Layout................................................................... 13 6.3 RecommendedOperatingConditions.......................5 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................13 6.5 ElectricalCharacteristics...........................................6 11.2 LayoutExample....................................................13 6.6 NoiseCharacteristics................................................6 12 DeviceandDocumentationSupport................. 14 6.7 OperatingCharacteristics..........................................6 12.1 DocumentationSupport........................................14 6.8 SwitchingCharacteristics:V =2.5V±0.2V........6 12.2 CommunityResources..........................................14 CC 6.9 SwitchingCharacteristics:V =3.3V±0.3V........7 12.3 Trademarks...........................................................14 CC 6.10 SwitchingCharacteristics:V =5V±0.5V.........7 12.4 ElectrostaticDischargeCaution............................14 CC 6.11 TypicalCharacteristics............................................8 12.5 Glossary................................................................14 7 ParameterMeasurementInformation..................9 13 Mechanical,Packaging,andOrderable Information........................................................... 14 8 DetailedDescription............................................ 10 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionM(June2013)toRevisionN Page • AddedDeviceInformationtable,PinFunctionstable,ESDRatingstable,ThermalInformationtable,Detailed Descriptionsection,ApplicationsandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection......1 • DeletedSN54LV244Apartnumberfromthedatasheet........................................................................................................ 1 • RemovedtheT =–40°Cto85°CtestconditionswiththesamevaluesastheT =–40°Cto125°CRecommended A A testconditionsintheElectricalCharacteristicsandSwitchingCharacteristicstables .......................................................... 6 • Removedtheword'Recommended'intheT =–40°Cto125°CRecommendedtestconditionsintheElectrical A CharacteristicsandSwitchingCharacteristicstables ............................................................................................................ 6 ChangesfromRevisionL(August2010)toRevisionM Page • ChangeddocumentformatfromQuicksilvertoDocZone ..................................................................................................... 1 • ChangedExtendedoperatingtemperaturerangeto125°C................................................................................................... 1 2 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 5 Pin Configuration and Functions DB,DGV,DW,NS,PWPackage 20-PinSSOP,TVSOP,SOIC,SO,TSSOP RGYPackage TopView 20-PinVQFNWithExposedThermalPad TopView 1OE 1 20 VCC OE CC 1A1 2 19 2OE 1 V 1 20 2Y4 3 18 1Y1 1A1 2 19 2OE 1A2 4 17 2A4 2Y4 3 18 1Y1 2Y3 5 16 1Y2 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 1A3 6 15 2A3 2Y2 7 14 1Y3 2Y2 7 14 1Y3 1A4 8 13 2A2 1A4 8 13 2A2 2Y1 9 12 1Y4 2Y1 9 12 1Y4 GND 10 11 2A1 10 11 D 1 N A G 2 PinFunctions PIN I/O DESCRIPTION NAME NO. 1A1 2 I Input 1A2 4 I Input 1A3 6 I Input 1A4 8 I Input 1OE 1 I Outputenable 1Y1 18 O Output 1Y2 16 O Output 1Y3 14 O Output 1Y4 12 O Output 2A1 11 I Input 2A2 13 I Input 2A3 15 I Input 2A4 17 I Input 2OE 19 I Outputenable 2Y1 9 O Output 2Y2 7 O Output 2Y3 5 O Output 2Y4 3 O Output GND 10 — Ground VCC 20 — Powerpin Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC V Inputvoltage(2) –0.5 7 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V O V Outputvoltage(2)(3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent V =0toV ±35 mA O O CC ContinuouscurrentthroughV orGND ±70 mA CC T Junctiontemperature –65 150 °C j T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto5.5-Vmaximum. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage 2 5.5 V CC V =2V 1.5 CC V =2.3Vto2.7V V ×0.7 CC CC V High-levelinputvoltage V IH V =3Vto3.6V V ×0.7 CC CC V =4.5Vto5.5V V ×0.7 CC CC V =2V 0.5 CC V =2.3Vto2.7V V ×0.3 CC CC V Low-levelinputvoltage V IL V =3Vto3.6V V ×0.3 CC CC V =4.5Vto5.5V V ×0.3 CC CC V Inputvoltage 0 5.5 V I Highorlowstate 0 V CC V Outputvoltage V O 3-state 0 5.5 V =2V –50 µA CC V =2.3Vto2.7V –2 CC I High-leveloutputcurrent OH V =3Vto3.6V –8 mA CC V =4.5Vto5.5V –16 CC V =2V 50 µA CC V =2.3Vto2.7V 2 CC I Low-leveloutputcurrent OL V =3Vto3.6V 8 mA CC V =4.5Vto5.5V 16 CC V =2.3Vto2.7V 200 CC Δt/Δv Inputtransitionriseorfallrate V =3Vto3.6V 100 ns/V CC V =4.5Vto5.5V 20 CC T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. 6.4 Thermal Information SN74LV244A DB DGV DW NS PW RGY THERMALMETRIC(1) UNIT (SSOP) (TVSOP) (SOIC) (SO) (TSSOP) (VQFN) 20PINS 20PINS 20PINS 20PINS 20PINS 20PINS Junction-to-ambientthermal R 94.7 115.9 79.4 76.9 102.6 34.9 °C/W θJA resistance Junction-to-case(top)thermal R 56.7 31.1 43.8 43.4 36.7 43.1 °C/W θJC(top) resistance R Junction-to-boardthermalresistance 49.9 57.4 47.2 44.5 53.6 12.7 °C/W θJB Junction-to-topcharacterization ψ 18.7 1.0 18.8 17.0 2.4 0.9 °C/W JT parameter Junction-to-boardcharacterization ψ 49.5 56.7 46.7 44.1 53.1 12.8 °C/W JB parameter Junction-to-case(bottom)thermal R n/a n/a n/a n/a n/a 7.8 °C/W θJC(bot) resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS VCC MIN TYP MAX UNIT 2Vto IOH=–50µA TA=–40°Cto125°C 5.5V VCC –0.1 VOH IOH=–2mA TA=–40°Cto125°C 2.3V 2 V IOH=–8mA TA=–40°Cto125°C 3V 2.48 IOH=16mA TA=–40°Cto125°C 4.5V 3.8 2Vto IOL=50µA TA=–40°Cto125°C 5.5V 0.1 VOL IOL=2mA TA=–40°Cto125°C 2.3V 0.4 V IOL=8mA TA=–40°Cto125°C 3V 0.44 IOL=16mA TA=–40°Cto125°C 4.5V 0.55 II VI=5.5VorGND TA=–40°Cto125°C 0to5.5V ±1 µA IOZ VO=VCCorGND TA=–40°Cto125°C 5.5V ±5 µA ICC V0I=VCCorGND,IO= TA=–40°Cto125°C 5.5V 20 µA Ioff VIorVO=0to5.5V TA=–40°Cto125°C 0 5 µA Ci VI=VCCorGND TA=–40°Cto125°C 3.3V 2.3 pF 6.6 Noise Characteristics V =3.3V,C =50pF,T =25°C(1) CC L A MIN TYP MAX UNIT V Quietoutput,maximumdynamic 0.55 V OL(P) V Quietoutput,minimumdynamic –0.5 V OL(V) V Quietoutput,minimumdynamic 2.9 V OH(V) V High-leveldynamicinputvoltage 2.31 V IH(D) V Low-leveldynamicinputvoltage 0.99 V IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 6.7 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 3.3V 14 C Powerdissipationcapacitance C =50pF,f=10MHz pF pd L 5V 16 6.8 Switching Characteristics: V = 2.5 V ± 0.2 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) CAPACITANCE TA=25°C 7.5(1) 12.5(1) tpd A Y CL=15pF ns TA=–40°Cto125°C 1 15 TA=25°C 8.9(1) 14.6(1) ten OE Y CL=15pF ns TA=–40°Cto125°C 1 17 TA=25°C 9.1(1) 14.1(1) tdis OE Y CL=15pF ns TA=–40°Cto125°C 1 16 TA=25°C 9.5(1) 15.3 tpd A Y CL=50pF ns TA=–40°Cto125°C 1 18 TA=25°C 10.8 17.8 ten OE Y CL=50pF ns TA=–40°Cto125°C 1 21 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 Switching Characteristics: V = 2.5 V ± 0.2 V (continued) CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) CAPACITANCE TA=25°C 13.4 19.2 tdis OE Y CL=50pF ns TA=–40°Cto125°C 1 21 TA=25°C 2 tsk(o) CL=50pF ns TA=–40°Cto125°C 2 6.9 Switching Characteristics: V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD MIN TYP MAX PARAMETER TESTCONDITIONS UNIT (INPUT) (OUTPUT) CAPACITANCE TA=25°C 5.4(1) 8.4(1) tpd A Y CL=15pF ns TA=–40°Cto125°C 1 10 TA=25°C 6.3(1) 10.6(1) ten OE Y CL=15pF ns TA=–40°Cto125°C 1 12.5 TA=25°C 7.6(1) 11.7(1) tdis OE Y CL=15pF ns TA=–40°Cto125°C 1 13 TA=25°C 6.8 11.9 tpd A Y CL=50pF ns TA=–40°Cto125°C 1 13.5 TA=25°C 7.8 14.1 ten OE Y CL=50pF ns TA=–40°Cto125°C 1 16 TA=25°C 11 16 tdis OE Y CL=50pF ns TA=–40°Cto125°C 1 18 TA=25°C 1.5 tsk(o) CL=50pF ns TA=–40°Cto125°C 1.5 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6.10 Switching Characteristics: V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure3) FROM TO LOAD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) CAPACITANCE TA=25°C 3.9(1) 5.5(1) tpd A Y CL=15pF ns TA=–40°Cto125°C 1 6.5 TA=25°C 4.5(1) 7.3(1) ten OE Y CL=15pF ns TA=–40°Cto125°C 1 8.5 TA=25°C 6.5(1) 12.2(1) tdis OE Y CL=15pF ns TA=–40°Cto125°C 1 13.5 TA=25°C 4.9 7.5 tpd A Y CL=50pF ns TA=–40°Cto125°C 1 8.5 TA=25°C 5.6 9.3 ten OE Y CL=50pF ns TA=–40°Cto125°C 1 10.5 TA=25°C 8.8 14.2 tdis OE Y CL=50pF ns TA=–40°Cto125°C 1 15.5 TA=25°C 1 tsk(o) ns TA=–40°Cto85°C 1 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com 6.11 Typical Characteristics e g e a g t t Volta put Vol u t p u n O I Output Current Input Current Figure1.InputVoltagevsInputCurrent Figure2.OutputVoltagevsOutputCurrent 8 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 7 Parameter Measurement Information CC From Output Test From Output RL= 1 kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see NoteA) (see NoteA) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATEAND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VCC VCC Output Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC In-Phase 50%VCC 50% VCC Waveform 1 50% VCC Output VOL S1 at VCC VOL+0.3VVOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Out-of-Phase 50% VCC 50% VCC Waveform 2 50% VCC VOH–0.3V Output VOL (seSe1 Nato GteN BD) ≈0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING A. C includesprobeandjigcapacitance. L B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutput control. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutput control. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,Z =50Ω,t ≤3ns, O r t ≤3ns. f D. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andt arethesameast . PZL PZH en G. t andt arethesameast . PHL PLH pd H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74LV244 devices are octal buffers grouped in fours, with each group having its own enable pin. The LV family supports high current drive of about 16 mA, thus making it suitable for driving digital signals over longer board lengths. This device is generally used to buffer or incorporate delays between the signals between two microcontrollerorperipheraldevices. 8.2 Functional Block Diagram 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 8.3 Feature Description The SN74LV244A, a part of LV family, can work over a wide voltage range from 2 V to 5.5 V. The device features a very low propagation delay of about 6.5 ns when enabled for 5-V V , which allows the device to be CC used for high-speed applications. The device supports a partial-power-down mode for low quiescent current application, thus making it the buffer of choice in power-efficient circuits. The I circuitry also disables the off outputs,preventingdamagingcurrentbackflowthroughthedeviceswhentheyarepowereddown. 8.4 Device Functional Modes The SN74LV244A devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must be tied to V through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of CC thedriver. Table1.FunctionTable INPUTS OUTPUTS OE A Y L L L L H H H X Z 10 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LV244A device can be used as an 8-channel buffer to drive signals from one controller to another device. Buffers are typically used for signals running on long traces on printed circuit boards or going through connectors linking two printed circuit boards together. Buffers are also used to create delay between the lines to match the edges of two clock or data signals. The high-current capability of the SN74LV244A device also allows acontrollertodriveLEDsupto16mA. 9.2 Typical Application 1OE 1 1A1 2 18 1B1 1A2 1B2 1A3 1B3 1A4 8 12 1B4 16 16 Controller 2OE Controller 19 Device /('¶V 2A1 11 9 2B1 2A2 2B2 2A3 2B3 2A4 17 3 2B4 Gnd V CC 0.1uF 10 20 Figure4. TypicalApplicationDiagram Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com Typical Application (continued) 9.2.1 DesignRequirements A 0.1-µF bypass capacitor must be placed between each V pin and GND. For best results, each capacitor CC mustbeplacedascloseaspossibletotheSN74LV244Adevice. 9.2.2 DetailedDesignProcedure 1. Recommendedinputconditions: – Forspecifiedhighandlowlevels,seeV andV inRecommendedOperatingConditions IH IL – Inputsandoutputsareovervoltagetolerant,whichallowsthemtogoashighas5.5VatanyvalidV CC 2. Recommendedoutputconditions: – LoadcurrentsmustnotexceedlimitsasmentionedinRecommendedOperatingConditions 3. Frequencyselectioncriterion: – Addedtraceresistanceorcapacitancecanreducemaximumfrequencycapability;uselayoutpracticesas directedinLayoutGuidelines 9.2.3 ApplicationCurve e g a t l o V Time Figure5.SN74LV244ATransientresponse 12 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

SN74LV244A www.ti.com SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply-voltage rating listed in the AbsoluteMaximumRatingstable. Each V terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled V , then a 0.01-μF or 0.022-μF CC capacitor is recommended for each V because the V pins are tied together internally. For devices with dual- CC CC supply pins operating at different voltages, for example V and V , a 0.1-µF bypass capacitor is recommended CC DD foreachsupplypin.Torejectdifferentfrequenciesofnoise,usemultiplebypasscapacitorsinparallel.Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel. For best results, the bypass capacitor must be installedascloseaspossibletothepowerterminal. 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight; therefore, some traces must turn corners. Figure 6 shows progressively better techniques of rounding corners. Onlythelastexample(BEST)maintainsconstanttracewidthandminimizesreflections. 11.2 Layout Example WORST BETTER BEST W 2 1W min. W Figure6. TraceExample Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LV244A

SN74LV244A SCLS383N–SEPTEMBER1997–REVISEDOCTOBER2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs,SCBA004 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 14 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV244A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV244A & no Sb/Br) SN74LV244APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWRG3 ACTIVE TSSOP PW 20 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) SN74LV244APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV244ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LV244A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LV244A : •Enhanced Product: SN74LV244A-EP Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LV244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LV244ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LV244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LV244APWRG3 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV244ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV244ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV244ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV244ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV244APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV244APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV244APWRG3 TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV244APWT TSSOP PW 20 250 367.0 367.0 38.0 SN74LV244ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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