Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs 1 Features 3 Description • 2-Vto5.5-VV Operation These octal buffers/drivers with inverted outputs are 1 CC designedfor2-Vto5.5-VV operation. • Maxt of6.5nsat5V CC pd The ’LV240A devices are designed specifically to • TypicalV (OutputGroundBounce) <0.8Vat OLP improve both the performance and density of 3-state V =3.3V,T =25°C CC A memory address drivers, clock drivers, and bus- • TypicalV (OutputV Undershoot)>2.3Vat OHV OH orientedreceiversandtransmitters. V =3.3V,T =25°C CC A These devices are organized as two 4-bit buffers/line • SupportMixed-ModeVoltageOperationonAll drivers with separate output-enable (OE) inputs. Ports When OE is low, the device passes inverted data • Latch-UpPerformanceExceeds250mAper from the A inputs to the Y outputs. When OE is high, JESD17 theoutputsareinthehigh-impedancestate. • I SupportsLiveInsertion,PartialPower-Down off DeviceInformation(1) Mode,andBackDriveProtection PARTNUMBER PACKAGE BODYSIZE(NOM) • ESDProtectionExceedsJESD22 TVSOP(14) 3.60mm×4.40mm – 2000-VHuman-BodyModel(A114-A) SOIC(14) 8.65mm×3.91mm – 200-VMachineModel(A115-A) LV240A SOP(14) 10.30mm×5.30mm – 1000-VCharged-DeviceModel(C101) SSOP(14) 6.20mm×5.30mm TSSOP(14) 5.00mm×4.40mm 2 Applications (1) For all available packages, see the orderable addendum at • Handset:Smartphone theendofthedatasheet. • NetworkSwitch • HealthandFitness/Wearables 4 Logic Diagram (Positive Logic) 1 1OE 2 18 1A1 1Y1 4 16 1A2 1Y2 6 14 1A3 1Y3 8 12 1A4 1Y4 19 2OE 11 9 2A1 2Y1 13 7 2A2 2Y2 15 5 2A3 2Y3 17 3 2A4 2Y4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription............................................ 10 2 Applications........................................................... 1 9.1 Overview.................................................................10 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.......................................10 4 LogicDiagram(PositiveLogic)............................ 1 9.3 FeatureDescription.................................................10 9.4 DeviceFunctionalModes........................................11 5 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 12 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................12 7 Specifications......................................................... 4 10.2 TypicalApplication ...............................................12 7.1 AbsoluteMaximumRatings .....................................4 11 PowerSupplyRecommendations..................... 14 7.2 ESDRatings..............................................................4 12 Layout................................................................... 14 7.3 RecommendedOperatingConditions.......................5 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................14 7.5 ElectricalCharacteristics...........................................6 12.2 LayoutExample....................................................14 7.6 SwitchingCharacteristics,V =2.5V±0.2V.........7 13 DeviceandDocumentationSupport................. 15 CC 7.7 SwitchingCharacteristics,V =3.3V±0.3V.........7 13.1 RelatedLinks........................................................15 CC 7.8 SwitchingCharacteristics,V =5V±0.5V............7 13.2 Trademarks...........................................................15 CC 7.9 NoiseCharacteristicsforSN74LV240A....................8 13.3 ElectrostaticDischargeCaution............................15 7.10 OperatingCharacteristics........................................8 13.4 Glossary................................................................15 7.11 TypicalCharacteristics............................................8 14 Mechanical,Packaging,andOrderable Information........................................................... 15 8 ParameterMeasurementInformation..................9 5 Revision History ChangesfromRevisionH(April2005)toRevisionI Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • Updatedoperatingfree-airtemperaturemaximumfrom85°Cto125°CforSN74LV240A ................................................... 5 2 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 6 Pin Configuration and Functions SN54LV240A:JorWPackage SN74LV240A:DB,DGV,DW,NS,orPWPackage SN54LV240A:FKPackage (TopView) (TopView) 4 1 E CE Y A O CO 1OE 1 20 VCC 2 1 1V 2 1A1 2 19 2OE 3 2 1 20 19 2Y4 3 18 1Y1 1A2 4 18 1Y1 1A2 4 17 2A4 2Y3 5 17 2A4 2Y3 5 16 1Y2 1A3 6 16 1Y2 1A3 6 15 2A3 2Y2 7 15 2A3 2Y2 7 14 1Y3 1A4 8 14 1Y3 9 10 11 12 13 1A4 8 13 2A2 2Y1 9 12 1Y4 1 D 14 2 GND 10 11 2A1 2Y GN 2A1Y 2A PinFunctions PIN I/O DESCRIPTION 1 1OE Outputenable1 2 1A1 1A1input 3 2Y4 2Y4output 4 1A2 1A2input 5 2Y3 2Y3output 6 1A3 1A3input 7 2Y2 2Y2output 8 1A4 1A4input 9 2Y1 2Y1output 10 GND Groundpin 11 2A1 2A1input 12 1Y4 1Y4output 13 2A2 2A2input 14 1Y3 1Y3output 15 2A3 2A3input 16 1Y2 1Y2output 17 2A4 2A4input 18 1Y1 1Y1output 19 2OE Outputenable2 20 VCC Powerpin Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperature(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC V Inputvoltage(2) –0.5 7 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V O V Outputvoltage(2) (3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent V =0toV –35 35 mA O O CC ContinuouscurrentthroughV orGND –70 70 mA CC T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thevalueislimitedto5.5-Vmaximum. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostatic Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) discharge Machinemodel(A115-A) 200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 7.3 Recommended Operating Conditions see (1) MIN MAX UNIT V Supplyvoltage 2 5.5 V CC V =2V 1.5 CC V =2.3to2.7V V ×0.7 CC CC V High-levelinputvoltage V IH V =3to3.6V V ×0.7 CC CC V =4.5to5.5V V ×0.7 CC CC V =2V 0.5 CC V =2.3to2.7V V ×0.3 CC CC V Low-levelinputvoltage V IL V =3to3.6V V ×0.3 CC CC V =4.5to5.5V V ×0.3 CC CC V Inputvoltage 0 5.5 V I Highorlowstate 0 V CC V Outputvoltage V O 3-state 0 5.5 V =2V –50 µA CC V =2.3to2.7V –2 CC I High-leveloutputcurrent OH V =3to3.6V –8 mA CC V =4.5to5.5V –16 CC V =2V 50 µA CC V =2.3to2.7V 2 CC I Low-leveloutputcurrent OL V =3to3.6V 8 mA CC V =4.5to5.5V 16 CC V =2.3to2.7V 200 CC Δt/Δv Inputtransitionriseorfallrate V =3to3.6V 100 ns/V CC V =4.5to5.5V 20 CC SN54LV240A –55 125 T Operatingfree-airtemperature °C A SN74LV240A –40 125 (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. 7.4 Thermal Information DW DB DGV NS PW THERMALMETRIC(1) UNIT 20PINS R Junction-to-ambientthermalresistance(2) 79.2 94.5 116.2 76.7 102.4 θJA R Junction-to-case(top)thermalresistance 43.7 56.4 31.2 43.2 36.5 θJC(top) R Junction-to-boardthermalresistance 47.0 49.7 57.7 44.2 53.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 18.6 18.5 0.9 16.8 2.4 JT ψ Junction-to-boardcharacterizationparameter 46.5 49.3 57.0 43.8 52.9 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I =–50µA 2to5.5V V –0.1 OH CC I =–2mA 2.3V 2 OH V V OH I =–8mA 3V 2.48 OH I =–16mA 4.5V 3.8 OH I =50µA 2to5.5V 0.1 OL I =2mA 2.3V 0.4 OL V V OL I =8mA 3V 0.44 OL I =16mA 4.5V 0.55 OL I V =5.5VorGND 0to5.5V ±1 µA I I I V =V orGND 5.5V ±5 µA OZ O CC I V =V orGND,I =0 5.5V 20 µA CC I CC O I V orV =0to5.5V 0 5 µA off I O C V =V orGND 3.3V 2.3 pF i I CC 6 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 7.6 Switching Characteristics, V = 2.5 V ±0.2 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(see) LOAD TA=25°C PARAMETER FROM(INPUT) TO(OUTPUT) MIN MAX UNIT CAPACITANCE MIN TYP MAX t A 6.3(1) 11.6(1) 1(2) 14(2) pd t OE Y C =15pF 8.5(1) 14.6(1) 1(2) 17(2) ns en L t OE 9.7(1) 14.1(1) 1(2) 16(2) dis t A 8.2 14.4 1 17 pd t OE Y 10.3 17.8 1 21 en C =50pF ns L t OE 14.2 19.2 1 21 dis t 2 2(3) sk(o) (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) ThisnoteappliestoSN54LV240Aonly:OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (3) ValueappliesforSN74LV240Aonly 7.7 Switching Characteristics, V = 3.3 V ±0.3 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(see) LOAD TA=25°C PARAMETER FROM(INPUT) TO(OUTPUT) MIN MAX UNIT CAPACITANCE MIN TYP MAX t A 4.6(1) 7.5(1) 1(2) 9(2) pd t OE Y C =15pF 6.2(1) 10.6(1) 1(2) 12.5(2) ns en L t OE 8.3(1) 12.5(1) 1(2) 13.5(2) dis t A 5.9 11 1 12.5 pd t OE Y 7.5 14.1 1 16 en C =50pF ns L t OE 11.8 15 1 17 dis t 1.5 1.5(3) sk(o) (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) ThisnoteappliestoSN54LV240Aonly:OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (3) ValueappliesforSN74LV240Aonly 7.8 Switching Characteristics, V = 5 V ±0.5 V CC overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(see) LOAD TA=25°C PARAMETER FROM(INPUT) TO(OUTPUT) MIN MAX UNIT CAPACITANCE MIN TYP MAX t A 3.4(1) 5.5(1) 1(2) 6.5(2) pd t OE Y C =15pF 4.6(1) 7.3(1) 1(2) 8.5(2) ns en L t OE 7.4(1) 12.2(1) 1(2) 13.5(2) dis t A 4.4 7.5 1 8.5 pd t OE Y 5.6 9.3 1 10.5 en C =50pF ns L t OE 9.7 14.2 1 15.5 dis t 1 1(3) sk(o) (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (2) ThisnoteappliestoSN54LV240Aonly:OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. (3) ThisvaluesappliesforSN74LV240Aonly Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 7.9 Noise Characteristics for SN74LV240A V =3.3V,C =50pF,T =25°C(see (1)) CC L A PARAMETER MIN TYP MAX UNIT V Quietoutput,maximumdynamicV 0.56 OL(P) OL V Quietoutput,minimumdynamicV –0.49 OL(V) OL V Quietoutput,minimumdynamicV 2.82 V OH(V) OH V High-leveldynamicinputvoltage 2.31 IH(D) V Low-leveldynamicinputvoltage 0.99 IL(D) (1) Characteristicsareforsurface-mountpackagesonly. 7.10 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 3.3V 14 C Powerdissipationcapacitance C =50pF,ƒ=10MHz pF pd L 5V 16.4 7.11 Typical Characteristics 6 7 5 6 5 4 s) s) 4 t (npd 3 t (npd 3 2 2 1 1 0 0 -100 -50 0 50 100 150 0 1 2 3 4 5 6 Temperature (°C) D001 VCC (V) D002 Figure1.t vsTemperatureat3.3-VV Figure2.t vsV at25°C pd CC pd CC 8 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 8 Parameter Measurement Information VCC From Output Test From Output RL= 1 kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see NoteA) (see NoteA) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATEAND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VCC VCC Output Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC In-Phase 50%VCC 50% VCC Waveform 1 50% VCC Output VOL S1 at VCC VOL+0.3VVOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Out-of-Phase 50% VCC 50% VCC Waveform 2 50% VCC VOH 0.3V Output VOL (seSe1 Nato GteN BD) ≈0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING A. C includesprobeandjigcapacitance. L B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutput control.Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbythe outputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,Z =50Ω,t ≤3ns,t O r f ≤3ns. D. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andtPZHarethesameast . PZL en G. t andt arethesameast . PHL PLH pd H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 9 Detailed Description 9.1 Overview Theseoctalbuffers/driverswithinvertedoutputsaredesignedfor2-Vto5.5-VV operation. CC The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory addressdrivers,clockdrivers,andbus-orientedreceiversandtransmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in thehigh-impedancestate. 9.2 Functional Block Diagram 1 1OE 2 18 1A1 1Y1 4 16 1A2 1Y2 6 14 1A3 1Y3 8 12 1A4 1Y4 19 2OE 11 9 2A1 2Y1 13 7 2A2 2Y2 15 5 2A3 2Y3 17 3 2A4 2Y4 Figure4. LogicDiagram(PositiveLogic) 9.3 Feature Description • Wideoperatingvoltagerangeoperatesfrom2-Vto5.5-Voperation • Allowdownvoltagetranslationinputsacceptvoltagesto5.5V • I featureallowsvoltagesontheinputsandoutputswhenV is0V off CC 10 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 9.4 Device Functional Modes Table1.FunctionTable (EachBuffer) INPUTS OUTPUT OE A Y L H L L L H H X Z Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information The SN74LV240A is a low-drive CMOS device that can be used for a multitude of bus interface type applications where the data needs to be retained or latched. It can produce 8 mA of drive current at 3.3 V making it ideal for driving multiple outputs and low-noise applications. The inputs are 5.5-V tolerant allowing it to translate down to V . CC 10.2 Typical Application Regulated 5 V V OE CC OE A1 Y1 Microcontroller System Logic Microcontroller or A8 Y8 LEDs System Logic GND Figure5. TypicalApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edgesintolightloadssoroutingandloadconditionsshouldbeconsideredtopreventringing. 10.2.2 DetailedDesignProcedure 1. Recommendedinputconditions – Risetimeandfalltimespecificationssee(Δt/ΔV)inRecommendedOperatingConditions. – Specifiedhighandlowlevels.See(V andV )inRecommendedOperatingConditions. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV CC 2. Recommendoutputconditions – Loadcurrentsshouldnotexceed35mAperoutputand70mAtotalforthepart – OutputsshouldnotbepulledaboveV CC 12 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 Typical Application (continued) 10.2.3 ApplicationCurve Figure6.SwitchingCharacteristicsComparison Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 www.ti.com 11 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in Recommended OperatingConditions. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, TI recommends 0.1 µF and if there are multiple V terminals, then TI recommends .01 µF or .022 µF for CC eachpowerterminal.Itisokaytoparallelmultiplebypasscapacitorstorejectdifferentfrequenciesofnoise.A0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminalaspossibleforbestresults. 12 Layout 12.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsshouldnoteverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more convenient. It is generally okay to float outputs unless the CC partisatransceiver.Ifthetransceiverhasanoutputenablepinitwilldisabletheoutputssectionofthepartwhen asserted.ThisdoesnotdisabletheinputsectionoftheIOssotheycannotfloatwhendisabled. 12.2 Layout Example V Input CC Unused Input Output Unused Input Output Input Figure7. LayoutRecommendation 14 SubmitDocumentationFeedback Copyright©1997–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV240A SN74LV240A

SN54LV240A,SN74LV240A www.ti.com SCLS384I–SEPTEMBER1997–REVISEDFEBRUARY2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54LV240A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LV240A Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1997–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN54LV240A SN74LV240A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV240ADBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ADW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ADWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240ANSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV240A & no Sb/Br) SN74LV240APW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240APWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) SN74LV240APWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV240ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LV240ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV240ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LV240ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LV240APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LV240APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV240APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74LV240APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV240ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV240ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV240ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV240ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV240APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV240APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV240APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV240APWT TSSOP PW 20 250 367.0 367.0 38.0 PackMaterials-Page2

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated