Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 SNx4LV165A Parallel-Load 8-Bit Shift Registers 1 Features 3 Description • 2-Vto5.5-VV Operation The ’LV165A devices are parallel-load, 8-bit shift 1 CC registersdesignedfor2-Vto5.5-VV operation. • Maxt of10.5nsat5V CC pd When the devices are clocked, data is shifted toward • SupportMixed-ModeVoltageOperationon the serial output Q . Parallel-in access to each stage AllPorts H is provided by eight individual direct data inputs that • I SupportsPartial-Power-DownMode off are enabled by a low level at the shift/load (SH/LD) Operation input. The ’LV165A devices feature a clock-inhibit • Latch-UpPerformanceExceeds250mAPer functionandacomplementedserialoutput, Q . H JESD17 Clocking is accomplished by a low-to-high transition • ESDProtectionExceedsJESD22 of the clock (CLK) input while SH/LD is held high and – 2000-VHuman-BodyModel(A114-A) clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low – 200-VMachineModel(A115-A) CLK and a low-to-high transition of CLK INH – 1000-VCharged-DeviceModel(C101) accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading 2 Applications is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held • IPRouters low, independently of the levels of CLK, CLK INH, or • EnterpriseSwitches SER. • AccessControlandSecurity:AccessKeypads These devices are fully specified for partial-power- andBiometrics down applications using I . The I circuitry disables off off • SmartMeters:PowerLineCommunication the outputs, preventing damaging current backflow throughthedeviceswhentheyarepowereddown. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SNx4LV165AD SOIC(16) 9.90mm×3.91mm SNx4LV165ADB SSOP(16) 6.20mm×5.30mm SNx4LV165ANS SO(16) 10.30mm×5.30mm SNx4LV165APW TSSOP(16) 5.00mm×4.40mm SNx4LV165ADGV TVSOP(16) 3.60mm×4.40mm SNx4LV165ARGY VQFN(16) 4.00mm×3.50mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. LogicDiagram(PositiveLogic) A B C D E F G H 11 12 13 14 3 4 5 6 1 SH/LD 15 CLKINH 2 CLK 9 S S S S S S S S Q 10 C1 C1 C1 C1 C1 C1 C1 C1 7 H SER 1D 1D 1D 1D 1D 1D 1D 1D QH R R R R R R R R 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................15 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................15 3 Description............................................................. 1 8.3 FeatureDescription.................................................16 8.4 DeviceFunctionalModes........................................17 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 18 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation............................................18 6 Specifications......................................................... 4 9.2 TypicalApplication..................................................18 6.1 AbsoluteMaximumRatings......................................4 10 PowerSupplyRecommendations..................... 20 6.2 ESDRatings..............................................................4 11 Layout................................................................... 20 6.3 RecommendedOperatingConditions.......................5 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................20 6.5 ElectricalCharacteristics...........................................6 11.2 LayoutExample....................................................20 6.6 TimingRequirements—V =2.5V±0.2V.............7 12 DeviceandDocumentationSupport................. 21 CC 6.7 TimingRequirements—V =3.3V±0.3V.............7 12.1 RelatedDocumentation.........................................21 CC 6.8 TimingRequirements—V =5V±0.5V................8 12.2 RelatedLinks........................................................21 CC 6.9 SwitchingCharacteristics—V =2.5V±0.2V.....10 12.3 ReceivingNotificationofDocumentationUpdates21 CC 6.10 SwitchingCharacteristics—V =3.3V±0.3V...11 12.4 CommunityResources..........................................21 CC 6.11 SwitchingCharacteristics—V =5V±0.5V......12 12.5 Trademarks...........................................................21 CC 6.12 OperatingCharacteristics......................................12 12.6 ElectrostaticDischargeCaution............................21 6.13 TypicalCharacteristics..........................................13 12.7 Glossary................................................................21 7 ParameterMeasurementInformation................14 13 Mechanical,Packaging,andOrderable Information........................................................... 21 8 DetailedDescription............................................ 15 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionN(July2013)toRevisionO Page • AddedApplicationssection,DeviceInformationtable,TableofContents,PinConfigurationandFunctionssection, Specificationssection,ESDRatingstable,ThermalInformationtable,TypicalCharacteristicssection,Detailed Descriptionsection,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection......1 ChangesfromRevisionM(December2010)toRevisionN Page • Extendedmaximumtemperatureoperatingrangefrom85°Cto125°C................................................................................. 5 2 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 5 Pin Configuration and Functions SN74LV165A:D,DB,DGV,NSorPWPackage SN74LV165A:RGYPackage SN54LV165A:JorWPackage 16-PinVQFN 16-PinSOIC,SSOP,TVSOP,SOP,TSSOP TopView TopView D SH/LD 1 16 V H/L CC CC S V CLK 2 15 CLK INH 1 16 E 3 14 D CLK 2 15 CLK INH F 4 13 C E 3 14 D G 5 12 B F 4 13 C H 6 11 A G 5 12 B Q 7 10 SER H H 6 11 A GND 8 9 QH QH 7 10 SER 8 9 D H N Q G PinFunctions PIN I/O DESCRIPTION NAME NO. A 11 I SerialinputA B 12 I SerialinputB C 13 I SerialinputC CLK 2 I Storageclock CLKINH 15 I Storageclock D 14 I SerialinputD E 3 I SerialinputE F 4 I SerialinputF G 5 I SerialinputG GND 8 — Groundpin H 6 I SerialinputH 7 Q O OutputH H 9 SH/LD 1 I LoadInput SER 10 I Serialinput V 16 — Powerpin CC Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings see (1) MIN MAX UNIT Supplyvoltage –0.5 7 V Inputvoltage(2) –0.5 7 V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V Outputvoltage (2)(3) –0.5 VCC+ V 0.5 Inputclampcurrent V <0 –20 mA I Outputclampcurrent V <0 –50 mA O Continuousoutputcurrent V =0toV ±25 mA O CC ContinuouscurrentthroughV orGND ±50 mA CC T Maximumvirtualjunctiontemperature 150 °C jmax T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto5.5Vmaximum. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage 2 5.5 V CC V =2V 1.5 CC V =2.3Vto2.7V V ×0.7 CC CC V High-levelinputvoltage V IH V =3Vto3.6V V ×0.7 CC CC V =4.5Vto5.5V V ×0.7 CC CC V =2V 0.5 CC V =2.3Vto2.7V V ×0.3 CC CC V Low-levelinputvoltage V IL V =3Vto3.6V V ×0.3 CC CC V =4.5Vto5.5V V ×0.3 CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =2V –50 µA CC V =2.3Vto2.7V –2 CC I High-leveloutputcurrent OH V =3Vto3.6V –6 mA CC V =4.5Vto5.5V –12 CC V =2V 50 µA CC V =2.3Vto2.7V 2 CC I Low-leveloutputcurrent OL V =3Vto3.6V 6 mA CC V =4.5Vto5.5V 12 CC V =2.3Vto2.7V 200 CC Δt/Δv Inputtransitionriseorfallrate V =3Vto3.6V 100 ns/V CC V =4.5Vto5.5V 20 CC SN54LV165A –55 125 T Operatingfree-airtemperature °C A SN74LV165A –40 125 (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeetheImplicationsofSloworFloating CC CMOSInputsapplicationreport. 6.4 Thermal Information SN74LV165A THERMALMETRIC(1) D(SOIC) DB(SSOP) NS(SO) PW DGV(TVSOP) RGY UNIT (TSSOP) (VQFN) 16PINS 16PINS 16PINS 16PINS 16PINS 16PINS Junction-to-ambient R 86.2 102.8 89.4 113.3 125.9 48.8 °C/W θJA thermalresistance Junction-to-case(top) R 46.1 53.3 47.9 48.3 51 46.7 °C/W θJC(top) thermalresistance Junction-to-boardthermal R 43.8 53.5 49.8 58.4 57.7 24.9 °C/W θJB resistance Junction-to-top ψ 13.2 16.6 16.6 6.4 5.7 2 °C/W JT characterizationparameter Junction-to-board ψ 43.5 52.9 49.5 57.8 57.2 24.9 °C/W JB characterizationparameter Junction-to-case(bottom) R N/A N/A N/A N/A N/A 11.7 °C/W θJC(bot) thermalresistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted).RecommendedT =–40°Cto+125°C A PARAMETER V T MIN TYP MAX UNIT CC A –55°Cto+125°C V –0.1 CC I =–50mA 2Vto5.5V –40°Cto+85°C –0.1 OH CC –40°Cto+125°C V –0.1 CC –55°Cto+125°C 2 I =–2mA 2.3V –40°Cto+85°C 2 OH –40°Cto+125°C 2 V V OH –55°Cto+125°C 2.48 I =–6mA 3V –40°Cto+85°C 2.48 OH –40°Cto+125°C 2.48 –55°Cto+125°C 3.8 I =–12mA 4.5V –40°Cto+85°C 3.8 OH –40°Cto+125°C 3.8 –55°Cto+125°C 0.1 I =50mA 2Vto5.5V –40°Cto+85°C 0.1 OL –40°Cto+125°C 0.1 –55°Cto+125°C 0.4 I =2mA 2.3V –40°Cto+85°C 0.4 OL –40°Cto+125°C 0.4 V V OL –55°Cto+125°C 0.44 I =6mA 3V –40°Cto+85°C 0.44 OL –40°Cto+125°C 0.44 –55°Cto+125°C 0.55 I =12mA 4.5V –40°Cto+85°C 0.55 OL –40°Cto+125°C 0.55 –55°Cto+125°C ±1 I V =5.5VorGND 0Vto5.5V –40°Cto+85°C ±1 µA I I –40°Cto+125°C ±1 –55°Cto+125°C 20 I V =V orGND,I =0 5.5V –40°Cto+85°C 20 µA CC I CC O –40°Cto+125°C 20 –55°Cto+125°C 5 I V orV =0to5.5V 0 –40°Cto+85°C 5 µA off I O –40°Cto+125°C 5 –55°Cto+125°C 1.7 C V =V orGND 3.3V –40°Cto+85°C 1.7 pF i I CC –40°Cto+125°C 1.7 6 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 6.6 Timing Requirements—V = 2.5 V ± 0.2 V CC overrecommendedoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted)(seeFigure2) CC PARAMETER TESTCONDITION TA MIN MAX UNIT 25°C 8.5 –55°Cto+125°C 9 CLKhighorlow –40°Cto+85°C 9 –40°Cto+125°C 9 tw Pulseduration ns 25°C 11 –55°Cto+125°C 13 SH/LDlow –40°Cto+85°C 13 –40°Cto+125°C 13 25°C 7 –55°Cto+125°C 8.5 SH/LDhighbeforeCLK↑ –40°Cto+85°C 8.5 –40°Cto+125°C 8.5 25°C 8.5 –55°Cto+125°C 9.5 SERbeforeCLK↑ –40°Cto+85°C 9.5 –40°Cto+125°C 9.5 tsu Setuptime ns 25°C 7 –55°Cto+125°C 7 CLKINHbeforeCLK↑ –40°Cto+85°C 7 –40°Cto+125°C 7 25°C 11.5 –55°Cto+125°C 12 DatabeforeSH/LD↑ –40°Cto+85°C 12 –40°Cto+125°C 12 25°C −1 –55°Cto+125°C 0 SERdataafterCLK↑ –40°Cto+85°C 0 –40°Cto+125°C 0 25°C 0 –55°Cto+125°C 0.5 th Holdtime ParalleldataafterSH/LD↑ ns –40°Cto+85°C 0.5 –40°Cto+125°C 0.5 25°C 0 –55°Cto+125°C 0 SH/LDhighafterCLK↑ –40°Cto+85°C 0 –40°Cto+125°C 0 6.7 Timing Requirements—V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure2) CC PARAMETER TESTCONDITION TA MIN MAX UNIT 25°C 6 –55°Cto+125°C 7 CLKhighorlow –40°Cto+85°C 7 –40°Cto+125°C 7 tw Pulseduration ns 25°C 7.5 –55°Cto+125°C 9 SH/LDlow –40°Cto+85°C 9 –40°Cto+125°C 9 Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com Timing Requirements—V = 3.3 V ± 0.3 V (continued) CC overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure2) CC PARAMETER TESTCONDITION TA MIN MAX UNIT 25°C 5 –55°Cto+125°C 6 SH/LDhighbeforeCLK↑ –40°Cto+85°C 6 –40°Cto+125°C 6 25°C 5 –55°Cto+125°C 6 SERbeforeCLK↑ –40°Cto+85°C 6 –40°Cto+125°C 6 tsu Setuptime ns 25°C 5 –55°Cto+125°C 5 CLKINHbeforeCLK↑ –40°Cto+85°C 5 –40°Cto+125°C 5 25°C 7.5 –55°Cto+125°C 8.5 DatabeforeSH/LD↑ –40°Cto+85°C 8.5 –40°Cto+125°C 8.5 25°C 0 –55°Cto+125°C 0 SERdataafterCLK↑ –40°Cto+85°C 0 –40°Cto+125°C 0 25°C 0.5 –55°Cto+125°C 0.5 th Holdtime ParalleldataafterSH/LD↑ ns –40°Cto+85°C 0.5 –40°Cto+125°C 0.5 25°C 0 –55°Cto+125°C 0 SH/LDhighafterCLK↑ –40°Cto+85°C 0 –40°Cto+125°C 0 6.8 Timing Requirements—V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure2) CC PARAMETER TESTCONDITION TA MIN MAX UNIT 25°C 4 –55°Cto+125°C 4 CLKhighorlow –40°Cto+85°C 4 –40°Cto+125°C 4 tw Pulseduration ns 25°C 5 –55°Cto+125°C 5 SH/LDlow –40°Cto+85°C 6 –40°Cto+125°C 6 8 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 Timing Requirements—V = 5 V ± 0.5 V (continued) CC overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure2) CC PARAMETER TESTCONDITION TA MIN MAX UNIT 25°C 4 –55°Cto+125°C 4 SH/LDhighbeforeCLK↑ –40°Cto+85°C 4 –40°Cto+125°C 4 25°C 4 –55°Cto+125°C 4 SERbeforeCLK↑ –40°Cto+85°C 4 –40°Cto+125°C 4 tsu Setuptime ns 25°C 3.5 –55°Cto+125°C 3.5 CLKINHbeforeCLK↑ –40°Cto+85°C 3.5 –40°Cto+125°C 3.5 25°C 5 –55°Cto+125°C 5 DatabeforeSH/LD↑ –40°Cto+85°C 5 –40°Cto+125°C 5 25°C 0.5 –55°Cto+125°C 0.5 SERdataafterCLK↑ –40°Cto+85°C 0.5 –40°Cto+125°C 0.5 25°C 1 –55°Cto+125°C 1 th Holdtime ParalleldataafterSH/LD↑ ns –40°Cto+85°C 1 –40°Cto+125°C 1 25°C 0.5 –55°Cto+125°C 0.5 SH/LDhighafterCLK↑ –40°Cto+85°C 0.5 –40°Cto+125°C 0.5 Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 6.9 Switching Characteristics—V = 2.5 V ± 0.2 V CC overoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted),(seeFigure2) CC PARAMETER FROM TO LOAD T MIN TYP MAX UNIT A (INPUT) (OUTPUT) CAP 25°C 50(1) 80(1) –55°Cto+125°C 45(1) C =15pF L –40°Cto+85°C 45 –40°Cto+125°C 45 f MHz max 25°C 40 65 –55°Cto+125°C 35 C =50pF L –40°Cto+85°C 35 –40°Cto+125°C 35 25°C 12.2(1) 19.8(1) –55°Cto+125°C 1(1) 22(1) CLK –40°Cto+85°C 1 22 –40°Cto+125°C 1 22 25°C 13.1(1) 21.5(1) –55°Cto+125°C 1(1) 23.5(1) t SH/LD Q orQ C =15pF ns pd H L –40°Cto+85°C 1 23.5 –40°Cto+125°C 1 23.5 25°C 12.9(1) 21.7(1) –55°Cto+125°C 1(1) 24(1) H –40°Cto+85°C 1 24 –40°Cto+125°C 1 24 25°C 15.3 23.3 –55°Cto+125°C 1 26 CLK –40°Cto+85°C 1 26 –40°Cto+125°C 1 26 25°C 16.1 25.1 –55°Cto+125°C 1 28 t SH/LD Q orQ C =50pF ns pd H L –40°Cto+85°C 1 28 –40°Cto+125°C 1 28 25°C 15.9 25.3 –55°Cto+125°C 1 28 H –40°Cto+85°C 1 28 –40°Cto+125°C 1 28 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 10 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 6.10 Switching Characteristics—V = 3.3 V ± 0.3 V CC overoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted),(seeFigure2) CC PARAMETER FROM TO LOAD T MIN TYP MAX UNIT A (INPUT) (OUTPUT) CAP 25°C 65(1) 115(1) –55°Cto+125°C 55(1) C =15pF L –40°Cto+85°C 55 –40°Cto+125°C 55 f MHz max 25°C 60 90 –55°Cto+125°C 50 C =50pF L –40°Cto+85°C 50 –40°Cto+125°C 50 25°C 8.6(1) 15.4(1) –55°Cto+125°C 1(1) 18(1) CLK –40°Cto+85°C 1 18 –40°Cto+125°C 1 18 25°C 9.1(1) 15.8(1) –55°Cto+125°C 1(1) 18.5(1) t SH/LD Q orQ C =15pF ns pd H L –40°Cto+85°C 1 18.5 –40°Cto+125°C 1 18.5 25°C 8.9(1) 14.1(1) –55°Cto+125°C 1(1) 16.5(1) H –40°Cto+85°C 1 16.5 –40°Cto+125°C 1 16.5 25°C 10.9 14.9 –55°Cto+125°C 1 16.9 CLK –40°Cto+85°C 1 16.9 –40°Cto+125°C 1 16.9 25°C 11.3 19.3 –55°Cto+125°C 1 22 t SH/LD Q orQ C =50pF ns pd H L –40°Cto+85°C 1 22 –40°Cto+125°C 1 22 25°C 11.1 17.6 –55°Cto+125°C 1 20 H –40°Cto+85°C 1 20 –40°Cto+125°C 1 20 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 6.11 Switching Characteristics—V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(seeFigure2) CC PARAMETER FROM TO LOAD T MIN TYP MAX UNIT A (INPUT) (OUTPUT) CAP 25°C 110(1) 165(1) –55°Cto+125°C 90(1) C =15pF L –40°Cto+85°C 90 –40°Cto+125°C 90 f MHz max 25°C 95 125 –55°Cto+125°C 85 C =50pF L –40°Cto+85°C 85 –40°Cto+125°C 85 25°C 6(1) 9.9(1) –55°Cto+125°C 1(1) 11.5(1) CLK –40°Cto+85°C 1 11.5 –40°Cto+125°C 1 11.5 25°C 6(1) 9.9(1) –55°Cto+125°C 1(1) 11.5(1) t SH/LD Q orQ C =15pF ns pd H L –40°Cto+85°C 1 11.5 –40°Cto+125°C 1 11.5 25°C 6(1) 9.9(1) –55°Cto+125°C 1(1) 10.5(1) H –40°Cto+85°C 1 10.5 –40°Cto+125°C 1 10.5 25°C 7.7 11.9 –55°Cto+125°C 1 13.5 CLK –40°Cto+85°C 1 13.5 –40°Cto+125°C 1 13.5 25°C 7.7 11.9 –55°Cto+125°C 1 13.5 t SH/LD Q orQ C =50pF ns pd H L –40°Cto+85°C 1 13.5 –40°Cto+125°C 1 13.5 25°C 7.6 11 –55°Cto+125°C 1 12.5 H –40°Cto+85°C 1 12.5 –40°Cto+125°C 1 12.5 (1) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 6.12 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 3.3V 36.1 C Powerdissipationcapacitance C =50pF f=10MHz pF pd L 5V 37.5 12 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 6.13 Typical Characteristics 16 15 CCLL==1550ppFF 14 13 s) 12 n d (typ 11 Tp 10 9 8 7 6 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 Vcc(V) D001 Figure1.T Typical(25°C)vsV PD cc Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 7 Parameter Measurement Information VCC FromOutput Test FromOutput RL=1kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (seeNoteA) (seeNoteA) tPHZ/tPZH GND OpenDrain VCC LOADCIRCUITFOR LOADCIRCUITFOR TOTEM-POLEOUTPUTS 3-STATEANDOPEN-DRAINOUTPUTS VCC TimingInput 50%VCC tw 0V th VCC tsu VCC Input 50%VCC 50%VCC DataInput 50%VCC 50%VCC 0V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPANDHOLDTIMES VCC Output VCC Input 50%VCC 50%VCC Control 50%VCC 50%VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC In-OPuhtapsuet 50%VCC 50%VCVCOL WaSv1efaotrVmCC1 50%VCC VOL+0.3VVOL (seeNoteB) tPHL tPLH tPZH tPHZ Output Out-of-OPuhtapsuet 50%VCC 50%VVCOVCLOH WSa1veaftoGrmND2 50%VCC VOH−0.3VV≈0OHV (seeNoteB) VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEANDDISABLETIMES INVERTINGANDNONINVERTINGOUTPUTS LOW-ANDHIGH-LEVELENABLING A. C includesprobeandjigcapacitance. L B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutput control. Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutput control. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,Z =50Ω,t ≤3ns, O r t ≤3ns. f D. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andt arethesameast . PZL PZH en G. t andt arethesameast . PHL PLH pd H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure2. LoadCircuitandVoltageWaveforms 14 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 8 Detailed Description 8.1 Overview The’LV165Adevicesareparallel-load,8-bitshiftregistersdesignedfor2-Vto5.5-VV operation. CC When the devices are clocked, data is shifted toward the serial output Q . Parallel-in access to each stage is H provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165Adevicesfeatureaclock-inhibitfunctionandacomplementedserialoutput, Q . H 8.2 Functional Block Diagram A B C D E F G H 11 12 13 14 3 4 5 6 1 SH/LD 15 CLKINH 2 CLK 9 S S S S S S S S Q 10 C1 C1 C1 C1 C1 C1 C1 C1 7 H SER 1D 1D 1D 1D 1D 1D 1D 1D QH R R R R R R R R PinnumbersshownarefortheD,DB,DGV,J,NS,PW,RGY,andWpackages. Figure3. LogicDiagram(PositiveLogic) Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com Functional Block Diagram (continued) CLK CLK INH SER L SH/LD A H B L C H Data D L Inputs E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit SerialShift Load Figure4. TypicalShift,Load,andInhibitSequences 8.3 Feature Description The wide operating range allows the device to be used in a variety of systems that use different logic levels. The low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce stabilizestheperformanceofnon-switchingoutputswhileanotheroutputisswitching. 16 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 8.4 Device Functional Modes Table1liststhefunctionalmodesofSNx4LV165A. Table1.DeviceFunctionalModes INPUTS OPERATION SH/LD CLK CLKINH L X X Parallelload H H X Q 0 H X H Q 0 H L ↑ Shift H ↑ L Shift Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74LV165A is a low drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low-drive and slow-edge rates minimize overshoot and undershoot on the outputs. 9.2 Typical Application CLK SN74LV165A SER CLK INH SH/LD A L H Dip B s s L H Switches r t e u C t p MCU s n D FPGA gi I CPU e l E Jumpers R e ll F t a if r G h a Any Slow-Changing S P H Logic Inputs Q H Q H Figure5. InputExpansionwithShiftRegisters 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that can exceed maximum limits. The high drive also creates fast edges into light loads so considerroutingandloadconditionstopreventringing. 9.2.2 DetailedDesignProcedure Recommendedinputconditions: • Risetimeandfalltimespecs.SeetheRecommendedOperatingConditions section,(Δt/ΔV) • Specifiedhighandlowlevel.SeetheRecommendedOperatingConditionssection,(V andV ) IH IL • Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV CC Recommendedoutputconditions: • Loadcurrentsmustnotexceed25mAperoutputand50mAtotalforthepart. • OutputsmustnotbepulledaboveV . CC 18 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 Typical Application (continued) 9.2.3 ApplicationCurves 16 26 15 CCLL==1550ppFF 24 CCLL == 1550ppFF 14 22 13 Tpd (ns)typ 111012 Tpd (ns)max 112680 9 14 8 12 7 6 10 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 Vcc(V) Vcc (V) D001 D001 Figure6.SwitchingCharacteristicsComparison Figure7.T vsV pd(max) CC Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A SCLS402O–APRIL1998–REVISEDNOVEMBER2016 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Absolute Maximum Ratings section. Each V terminal must have a good bypass capacitor to prevent power CC disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple V CC terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for bestresults. 11 Layout 11.1 Layout Guidelines Whenusingmultiplebitlogicdevicesinputsmustneverfloat. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or V whichever make more sense or is more convenient. Floating outputs is generally CC acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it disables the outputs section of the part when asserted. This does not disable the input section of the IOs so they also cannot float whendisabled. 11.2 Layout Example Figure8. LayoutExample 20 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV165A SN74LV165A

SN54LV165A,SN74LV165A www.ti.com SCLS402O–APRIL1998–REVISEDNOVEMBER2016 12 Device and Documentation Support 12.1 Related Documentation Forrelateddocumentationseethefollowing: • Power-UpBehaviorofClockedDevices • IntroductiontoLogic 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54LV165A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LV165A Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any reviseddocument. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SN54LV165A SN74LV165A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV165AD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADRG3 ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ANSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV165A & no Sb/Br) SN74LV165APW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165APWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165APWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165APWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV165A & no Sb/Br) SN74LV165ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LV165A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV165ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LV165A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LV165A : •Enhanced Product: SN74LV165A-EP Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV165ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV165ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV165ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV165ADRG3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV165ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV165ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV165APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165APWRG3 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV165ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV165ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV165ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV165ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV165ADRG3 SOIC D 16 2500 364.0 364.0 27.0 SN74LV165ADRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74LV165ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV165APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV165APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV165APWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV165APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV165APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV165ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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