ICGOO在线商城 > 集成电路(IC) > 逻辑 - 信号开关,多路复用器,解码器 > SN74LV157APWG4
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SN74LV157APWG4产品简介:
ICGOO电子元器件商城为您提供SN74LV157APWG4由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74LV157APWG4价格参考。Texas InstrumentsSN74LV157APWG4封装/规格:逻辑 - 信号开关,多路复用器,解码器, Multiplexer 4 x 2:1 16-TSSOP。您可以下载SN74LV157APWG4参考资料、Datasheet数据手册功能说明书,资料中有SN74LV157APWG4 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC DATASELCT/MUX 2-1 QUAD16TSSOP编码器、解码器、复用器和解复用器 Quad 2-1-Line Data Selectors/Mltplxrs |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,编码器、解码器、复用器和解复用器,Texas Instruments SN74LV157APWG474LV |
数据手册 | |
产品型号 | SN74LV157APWG4 |
产品 | Selectors / Multiplexers |
产品种类 | 编码器、解码器、复用器和解复用器 |
传播延迟时间 | 19.5 ns |
位数 | 4 |
供应商器件封装 | 16-TSSOP |
包装 | 管件 |
单位重量 | 62 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Tube |
封装/外壳 | 16-TSSOP(0.173",4.40mm 宽) |
封装/箱体 | TSSOP-16 |
工作温度 | -40°C ~ 85°C |
工作温度范围 | - 40 C to + 85 C |
工作电压 | 2 V to 5.5 V |
工厂包装数量 | 90 |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
标准包装 | 90 |
独立电路 | 1 |
电压-电源 | 2 V ~ 5.5 V |
电压源 | 单电源 |
电流-输出高,低 | 12mA,12mA |
电源电压-最大 | 5.5 V |
电源电压-最小 | 2 V |
电路 | 4 x 2:1 |
类型 | 多路复用器 |
系列 | SN74LV157A |
输入/输出线数量 | 2 / 1 |
输入线路数量 | 2 |
输出线路数量 | 1 |
逻辑系列 | LV-A |
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 (cid:1) 2-V to 5.5-V V Operation SN54LV157A...J OR W PACKAGE CC (cid:1) SN74LV157A...D, DB, DGV, NS, OR PW PACKAGE Max tpd of 7.5 ns at 5 V (TOP VIEW) (cid:1) Typical V (Output Ground Bounce) OLP <0.8 V at VCC, TA = 25°C A/B 1 16 VCC (cid:1) Typical V (Output V Undershoot) 1A 2 15 G OHV OH >2.3 V at V , T = 25°C 1B 3 14 4A CC A (cid:1) I Supports Partial-Power-Down-Mode 1Y 4 13 4B off Operation 2A 5 12 4Y (cid:1) 2B 6 11 3A Latch-Up Performance Exceeds 100 mA Per 2Y 7 10 3B JESD 78, Class II (cid:1) GND 8 9 3Y ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN54LV157A...FK PACKAGE (TOP VIEW) − 1000-V Charged-Device Model (C101) description/ordering information 1A A/B NC VCCG 3 2 1 20 19 The ’LV157A devices are quadruple 2-line to 1B 4 18 4A 1-line data selectors/multiplexers designed for 1Y 5 17 4B 2-V to 5.5-V VCC operation. NC 6 16 NC These devices contain inverters and drivers to 2A 7 15 4Y supply full data selection to the four output gates. 2B 8 14 3A 9 10 1112 13 A separate strobe (G) input is provided. A 4-bit word is selected from one of two sources and is Y D CY B 2 N N3 3 routed to the four outputs. The ’LV157A devices G present true data. NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube of 40 SN74LV157AD SSOOIICC −− DD LLVV115577AA Reel of 2500 SN74LV157ADR SOP − NS Reel of 2000 SN74LV157ANSR 74LV157A SSOP − DB Reel of 2000 SN74LV157ADBR LV157A −−4400°°CC ttoo 8855°°CC Tube of 90 SN74LV157APW TTSSSSOOPP −− PPWW Reel of 2000 SN74LV157APWR LLVV115577AA Reel of 250 SN74LV157APWT TVSOP − DGV Reel of 2000 SN74LV157ADGVR LV157A CDIP − J Tube of 25 SNJ54LV157AJ SNJ54LV157AJ −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54LV157AW SNJ54LV157AW LCCC − FK Tube of 55 SNJ54LV157AFK SNJ54LV157AFK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:12)(cid:2)(cid:5)(cid:16)(cid:1)(cid:1) (cid:21)(cid:20)(cid:26)(cid:16)(cid:14)(cid:27)(cid:19)(cid:1)(cid:16) (cid:2)(cid:21)(cid:20)(cid:16)(cid:13) (cid:28)(cid:29)(cid:30)(cid:31) !"#$%&’(cid:28) #"’(cid:28)((cid:30)’(cid:31) (cid:15)(cid:14)(cid:21)(cid:13)(cid:12)(cid:22)(cid:20)(cid:19)(cid:21)(cid:2) Copyright 2005, Texas Instruments Incorporated (cid:13)(cid:9)(cid:20)(cid:9) (cid:30)’)"*%((cid:28)(cid:30)"’ #$**&’(cid:28) ((cid:31) ") +$,-(cid:30)#((cid:28)(cid:30)"’ !((cid:28)&. (cid:15)*"!$#(cid:28)(cid:31) #"’)"*% (cid:28)" (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) +&* (cid:28)(cid:29)& (cid:28)&*%(cid:31) ") (cid:20)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) (cid:31)(cid:28)(’!(*! 0(**(’(cid:28)1. (cid:15)*"!$#(cid:28)(cid:30)"’ +*"#&(cid:31)(cid:31)(cid:30)’2 !"&(cid:31) ’"(cid:28) ’&#&(cid:31)(cid:31)(*(cid:30)-1 (cid:30)’#-$!& (cid:28)&(cid:31)(cid:28)(cid:30)’2 ") (-- +(*(%&(cid:28)&*(cid:31). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OOUUTTPPUUTT SSEELLEECCTT DATA GG YY A/B A B H X X X L L L L X L L L H X H L H X L L L H X H H logic diagram (positive logic) 2 1A 4 1Y 3 1B 5 2A 7 2Y 6 2B 11 3A 9 3Y 10 3B 14 4A 12 4Y 13 4B 15 G 1 A/B Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V + 0.5 V O CC Output voltage range applied in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V O Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV157A SN74LV157A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 5.5 2 5.5 V VCC = 2 V 1.5 1.5 VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 VV VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7 VCC = 2 V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 VV VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2 V −50 −50 µA VCC = 2.3 V to 2.7 V −2 −2 IIOOHH HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V −6 −6 mmAA VCC = 4.5 V to 5.5 V −12 −12 VCC = 2 V 50 50 µA VCC = 2.3 V to 2.7 V 2 2 IIOOLL LLooww--lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V 6 6 mmAA VCC = 4.5 V to 5.5 V 12 12 VCC = 2.3 V to 2.7 V 200 0 200 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee VCC = 3 V to 3.6 V 100 0 100 nnss//VV VCC = 4.5 V to 5.5 V 20 0 20 TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV157A SN74LV157A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN TYP MAX IOH = −50 µA 2 V to 5.5 V VCC−0.1 VCC−0.1 IOH = −2 mA 2.3 V 2 2 VVOOHH VV IOH = −6 mA 3 V 2.48 2.48 IOH = −12 mA 4.5 V 3.8 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 VVOOLL VV IOL = 6 mA 3 V 0.44 0.44 IOL = 12 mA 4.5 V 0.55 0.55 II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA Ioff VI or VO = 0 to 5.5 V 0 5 5 µA Ci VI = VCC or GND 3.3 V 1.7 1.7 pF (cid:15)(cid:14)(cid:21)(cid:13)(cid:12)(cid:22)(cid:20) (cid:15)(cid:14)(cid:16)(cid:6)(cid:19)(cid:16)(cid:27) (cid:30)’)"*%((cid:28)(cid:30)"’ #"’#&*’(cid:31) +*"!$#(cid:28)(cid:31) (cid:30)’ (cid:28)(cid:29)& )"*%((cid:28)(cid:30)3& "* !&(cid:31)(cid:30)2’ +(cid:29)((cid:31)& ") !&3&-"+%&’(cid:28). (cid:22)(cid:29)(*(#(cid:28)&*(cid:30)(cid:31)(cid:28)(cid:30)# !((cid:28)( (’! "(cid:28)(cid:29)&* (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) (*& !&(cid:31)(cid:30)2’ 2"(-(cid:31). (cid:20)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) *&(cid:31)&*3&(cid:31) (cid:28)(cid:29)& *(cid:30)2(cid:29)(cid:28) (cid:28)" #(cid:29)(’2& "* !(cid:30)(cid:31)#"’(cid:28)(cid:30)’$& (cid:28)(cid:29)&(cid:31)& +*"!$#(cid:28)(cid:31) 0(cid:30)(cid:28)(cid:29)"$(cid:28) ’"(cid:28)(cid:30)#&. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, V = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV157A SN74LV157A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 7.4* 15.9* 1* 19.5* 1 19.5 ttppdd A/B Y CCLL == 1155 ppFF 7.9* 19.4* 1* 23.5* 1 23.5 nnss G Y 7.8* 19.8* 1* 24* 1 24 A or B Y 9.4 18.8 1 22 1 22 ttppdd A/B Y CCLL == 5500 ppFF 10.8 22.3 1 26 1 26 nnss G Y 9.6 22.7 1 26.5 1 26.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV157A SN74LV157A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 5.2* 9.7* 1* 11.5* 1 11.5 ttppdd A/B Y CCLL == 1155 ppFF 5.8* 13.2* 1* 15.5* 1 15.5 nnss G Y 5.5* 13.6* 1* 16* 1 16 A or B Y 6.7 13.2 1 15 1 15 ttppdd A/B Y CCLL == 5500 ppFF 7.6 16.7 1 19 1 19 nnss G Y 7 17.1 1 19.5 1 19.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV157A SN74LV157A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 3.6* 6.4* 1* 7.5* 1 7.5 ttppdd A/B Y CCLL == 1155 ppFF 4.1* 8.1* 1* 9.5* 1 9.5 nnss G Y 3.8* 8.6* 1* 10* 1 10 A or B Y 4.8 8.4 1 9.5 1 9.5 ttppdd A/B Y CCLL == 5500 ppFF 5.4 10.1 1 11.5 1 11.5 nnss G Y 5 10.6 1 12 1 12 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV157A PPAARRAAMMEETTEERR UUNNIITT MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.1 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.2 V VIH(D) High-level dynamic input voltage 2.31 V VIL(D) Low-level dynamic input voltage 0.99 V NOTE 5: Characteristics are for surface-mount packages only. (cid:15)(cid:14)(cid:21)(cid:13)(cid:12)(cid:22)(cid:20) (cid:15)(cid:14)(cid:16)(cid:6)(cid:19)(cid:16)(cid:27) (cid:30)’)"*%((cid:28)(cid:30)"’ #"’#&*’(cid:31) +*"!$#(cid:28)(cid:31) (cid:30)’ (cid:28)(cid:29)& )"*%((cid:28)(cid:30)3& "* !&(cid:31)(cid:30)2’ +(cid:29)((cid:31)& ") !&3&-"+%&’(cid:28). (cid:22)(cid:29)(*(#(cid:28)&*(cid:30)(cid:31)(cid:28)(cid:30)# !((cid:28)( (’! "(cid:28)(cid:29)&* (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) (*& !&(cid:31)(cid:30)2’ 2"(-(cid:31). (cid:20)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) *&(cid:31)&*3&(cid:31) (cid:28)(cid:29)& *(cid:30)2(cid:29)(cid:28) (cid:28)" #(cid:29)(’2& "* !(cid:30)(cid:31)#"’(cid:28)(cid:30)’$& (cid:28)(cid:29)&(cid:31)& +*"!$#(cid:28)(cid:31) 0(cid:30)(cid:28)(cid:29)"$(cid:28) ’"(cid:28)(cid:30)#&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS VCC TYP UNIT 3.3 V 12.1 CCppdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee CCLL == 5500 ppFF,, ff == 1100 MMHHzz ppFF 5 V 13.1 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:11)(cid:12)(cid:9)(cid:13)(cid:14)(cid:12)(cid:15)(cid:5)(cid:16) (cid:17)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:20)(cid:21) (cid:7)(cid:18)(cid:5)(cid:19)(cid:2)(cid:16) (cid:13)(cid:9)(cid:20)(cid:9) (cid:1)(cid:16)(cid:5)(cid:16)(cid:22)(cid:20)(cid:21)(cid:14)(cid:1)(cid:23)(cid:24)(cid:12)(cid:5)(cid:20)(cid:19)(cid:15)(cid:5)(cid:16)(cid:25)(cid:16)(cid:14)(cid:1) SCLS397F − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC InO-Puhtapsuet 50% VCC 50% VCVCOL WSav1e afto VrmC C1 50% VCC VOL + 0.3 VVOL (see Note B) tPHL tPLH tPZH tPHZ Output Out-of-Phase 50% VCC 50% VCVCOH Waveform 2 50% VCC VOH − 0.3 VVOH Output VOL (seSe1 Nato GteN BD) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV157AD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157ADBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157ADR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157ANSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 74LV157A & no Sb/Br) SN74LV157APW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) SN74LV157APWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV157A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV157ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV157ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV157ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV157APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV157ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV157ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV157ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV157APWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2
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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com
EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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