SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 (cid:2) (cid:2) 2-V to 5.5-V V Operation I Supports Partial-Power-Down Mode CC off (cid:2) Max tpd of 7.5 ns at 5 V Operation (cid:2) Support Mixed-Mode Voltage Operation on (cid:2) Latch-Up Performance Exceeds 250 mA Per All Ports JESD 17 (cid:2) (cid:2) ESD Protection Exceeds JESD 22 Designed Specifically for High-Speed − 2000-V Human-Body Model (A114-A) Memory Decoders and Data-Transmission − 200-V Machine Model (A115-A) Systems (cid:2) − 1000-V Charged-Device Model (C101) Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception SN54LV139A...J OR W PACKAGE SN74LV139A...RGY PACKAGE SN54LV139A...FK PACKAGE SN74LV139A...D, DB, DGV, NS, (TOP VIEW) (TOP VIEW) OR PW PACKAGE C (TOP VIEW) G CC 1A 1G NC VC2G 1 V 1G 1 16 VCC 1 16 3 2 1 20 19 1B 4 18 2A 1A 2 15 2G 1A 2 15 2G 1Y0 5 17 2B 1B 3 14 2A 1B 3 14 2A NC 6 16 NC 1Y0 4 13 2B 1Y0 4 13 2B 1Y1 7 15 2Y0 1Y1 5 12 2Y0 1Y1 5 12 2Y0 1Y2 8 14 2Y1 1Y2 6 11 2Y1 1Y2 6 11 2Y1 9 10 1112 13 1Y3 7 10 2Y2 1Y3 7 10 2Y2 GND 8 9 2Y3 8 9 Y3ND NC Y3Y2 D 3 1G 22 N Y G 2 NC − No internal connection description/ordering information The ’LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V V operation. CC ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Reel of 1000 SN74LV139ARGYR LV139A Tube of 40 SN74LV139AD SSOOIICC − DD LLVV113399AA Reel of 2500 SN74LV139ADR SOP − NS Reel of 2000 SN74LV139ANSR 74LV139A −4400°CC ttoo 8855°CC SSOP − DB Reel of 2000 SN74LV139ADBR LV139A Tube of 90 SN74LV139APW TTSSSSOOPP − PPWW Reel of 2000 SN74LV139APWR LLVV113399AA Reel of 250 SN74LV139APWT TVSOP − DGV Reel of 2000 SN74LV139ADGVR LV139A CDIP − J Tube of 25 SNJ54LV139AJ SNJ54LV139AJ −55°C to 125°C CFP − W Tube of 150 SNJ54LV139AW SNJ54LV139AW LCCC − FK Tube of 55 SNJ54LV139AFK SNJ54LV139AFK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright © 2005, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OOUUTTPPUUTTSS SELECT GG B A Y0 Y1 Y2 Y3 H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) 4 1Y0 1 1G 5 1Y1 6 1Y2 2 1A 7 3 1Y3 1B 12 2Y0 15 2G 11 2Y1 10 2Y2 14 2A 9 13 2Y3 2B Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV139A SN74LV139A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 2 5.5 2 5.5 V VCC = 2 V 1.5 1.5 VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7 VVIH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 VV VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7 VCC = 2 V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3 VVIL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 VV VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3 VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2 V −50 −50 μA VCC = 2.3 V to 2.7 V −2 −2 IIOH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V −6 −6 mmAA VCC = 4.5 V to 5.5 V −12 −12 VCC = 2 V 50 50 μA VCC = 2.3 V to 2.7 V 2 2 IIOL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V 6 6 mmAA VCC = 4.5 V to 5.5 V 12 12 VCC = 2.3 V to 2.7 V 200 200 ΔΔtt//ΔΔvv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee VCC = 3 V to 3.6 V 100 100 nnss//VV VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV139A SN74LV139A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCC MIN TYP MAX MIN TYP MAX UUNNIITT IOH = −50 μA 2 V to 5.5 V VCC−0.1 VCC−0.1 IOH = −2 mA 2.3 V 2 2 VVOH IOH = −6 mA 3 V 2.48 2.48 VV IOH = −12 mA 4.5 V 3.8 3.8 IOL = 50 μA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 VVOL IOL = 6 mA 3 V 0.44 0.44 VV IOL = 12 mA 4.5 V 0.55 0.55 II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 μA ICC VI = VCC or GND, IO = 0 5.5 V 20 20 μA Ioff VI or VO = 0 to 5.5 V 0 5 5 μA Ci VI = VCC or GND 3.3 V 1.9 1.9 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, V = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV139A SN74LV139A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 7.7* 17.6* 1* 21* 1 21 ttpd G Y CCL = 1155 ppFF 7.4* 15.8* 1* 19* 1 19 nnss A or B Y 10.2 22.5 1 26.5 1 26.5 ttpd CCL == 5500 ppFF nnss G Y 9.9 20.2 1 24 1 24 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV139A SN74LV139A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 5.3* 11* 1* 13* 1 13 ttpd G Y CCL = 1155 ppFF 5.1* 9.2* 1* 11* 1 11 nnss A or B Y 7.3 14.5 1 16.5 1 16.5 ttpd CCL == 5500 ppFF nnss G Y 7 12.7 1 14.5 1 14.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C SN54LV139A SN74LV139A PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX A or B Y 3.7* 7.2* 1* 8.5* 1 8.5 ttpd G Y CCL = 1155 ppFF 3.5* 6.3* 1* 7.5* 1 7.5 nnss A or B Y 5.2 9.2 1 10.5 1 10.5 ttpd CCL == 5500 ppFF nnss G Y 4.9 8.3 1 9.5 1 9.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS VCC TYP UNIT 3.3 V 17.3 CCpd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee CCL == 5500 ppFF, ff == 1100 MMHHzz ppFF 5 V 18.2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396I − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC Output VCC Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC InO-Puhtapsuet 50% VCC 50% VCVCOL WaSv1e faot rVmC C1 50% VCC VOL + 0.3 V VOL (see Note B) tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH − 0.3 VV≈0O HV VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV139AD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139ADBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139ADR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139ANSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 74LV139A & no Sb/Br) SN74LV139ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 74LV139A & no Sb/Br) SN74LV139APW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139APWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139APWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV139A & no Sb/Br) SN74LV139ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LV139A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV139ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV139ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV139APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV139APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV139ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV139ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV139ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV139APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV139APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV139ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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