SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 (cid:1) Qualified for Automotive Applications PW PACKAGE (cid:1) (TOP VIEW) Typical V (Output Ground Bounce) OLP <0.8 V at VCC = 3.3 V, TA = 25°C 1A 1 14 VCC (cid:1) Typical VOHV (Output VOH Undershoot) 1B 2 13 4B >2.3 V at VCC = 3.3 V, TA = 25°C 1Y 3 12 4A (cid:1) Supports Mixed-Mode Voltage Operation on 2A 4 11 4Y All Ports 2B 5 10 3B (cid:1) I Supports Partial-Power-Down Mode 2Y 6 9 3A off Operation GND 7 8 3Y (cid:1) Latch-Up Performance Exceeds 250 mA Per JESD 17 (cid:1) ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V V operation. CC The SN74LV08A performs the Boolean function Y(cid:1)A•BorY(cid:1)A(cid:2)B in positive logic. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION† ORDERABLE TOP-SIDE TA PACKAGE‡ PART NUMBER MARKING −40°C to 105°C TSSOP − PW Tape and reel SN74LV08ATPWRQ1 LV08ATQ †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H H H L X L X L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2008, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 1 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 2 5.5 V VCC = 2 V 1.5 VCC = 2.3 V to 2.7 V VCC ×0.7 VVIH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.7 VV VCC = 4.5 V to 5.5 V VCC ×0.7 VCC = 2 V 0.5 VCC = 2.3 V to 2.7 V VCC ×0.3 VVIL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 3 V to 3.6 V VCC ×0.3 VV VCC = 4.5 V to 5.5 V VCC ×0.3 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2 V −50 µA VCC = 2.3 V to 2.7 V −2 IIOH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V −6 mmAA VCC = 4.5 V to 5.5 V −12 VCC = 2 V 50 µA VCC = 2.3 V to 2.7 V 2 IIOL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 3 V to 3.6 V 6 mmAA VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee oorr ffaallll rraattee VCC = 3 V to 3.6 V 100 nnss//VV VCC = 4.5 V to 5.5 V 20 TA Operating free-air temperature −40 105 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IOH = −50 µA 2 V to 5.5 V VCC−0.1 IOH = −2 mA 2.3 V 2 VVOH IOH = −6 mA 3 V 2.48 VV IOH = −12 mA 4.5 V 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 IOL = 2 mA 2.3 V 0.4 VVOL IOL = 6 mA 3 V 0.44 VV IOL = 12 mA 4.5 V 0.55 II VI = 5.5 V or GND 0 to 5.5 V ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 20 µA Ioff VI or VO = 0 to 5.5 V 0 5 µA 3.3 V 3.3 CCi VVI == VVCC oorr GGNNDD ppFF 5 V 3.3 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 3 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX tpd A or B Y CL = 50 pF 7.5 12.3 1 16 ns switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO LLOOAADD TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX tpd A or B Y CL = 50 pF 5.5 7.9 1 12 ns noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.1 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.1 V VIH(D) High-level dynamic input voltage 2.31 V VIL(D) Low-level dynamic input voltage 0.99 V NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS VCC TYP UNIT 3.3 V 8 CCpd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee CCL == 5500 ppFF, ff == 1100 MMHHzz ppFF 5 V 10 4 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

SN74LV08A-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC Output VCC Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC InO-Puhtapsuet 50% VCC 50% VCVCOL WaSv1e faot rVmC C1 50% VCC VOL + 0.3 V VOL (see Note B) tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH − 0.3 VV≈0O HV VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 5 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV08ATPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 LV08ATQ & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 OTHER QUALIFIED VERSIONS OF SN74LV08A-Q1 : •Catalog: SN74LV08A •Enhanced Product: SN74LV08A-EP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV08ATPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV08ATPWRG4Q1 TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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