SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 (cid:0) Choice of Eight Latches or Eight D-Type SN54LS373, SN54LS374, SN54S373, Flip-Flops in a Single Package SN54S374 . . . J OR W PACKAGE (cid:0) SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE 3-State Bus-Driving Outputs SN74LS374 . . . DB, DW, N, OR NS PACKAGE (cid:0) Full Parallel Access for Loading SN74S373 . . . DW OR N PACKAGE (cid:0) (TOP VIEW) Buffered Control Inputs (cid:0) Clock-Enable Input Has Hysteresis to OC 1 20 VCC Improve Noise Rejection (’S373 and ’S374) 1Q 2 19 8Q (cid:0) P-N-P Inputs Reduce DC Loading on Data 1D 3 18 8D Lines (’S373 and ’S374) 2D 4 17 7D 2Q 5 16 7Q description 3Q 6 15 6Q 3D 7 14 6D These 8-bit registers feature 3-state outputs 4D 8 13 5D designed specifically for driving highly capacitive 4Q 9 12 5Q or relatively low-impedance loads. The GND 10 11 C† high-impedance 3-state and increased high-logic-level drive provide these registers with †C for ’LS373 and ’S373; CLK for ’LS374 and ’S374. the capability of being connected directly to and driving the bus lines in a bus-organized system SN54LS373, SN54LS374, SN54S373, SN54S374 . . . FK PACKAGE without need for interface or pullup components. (TOP VIEW) These devices are particularly attractive for implementing buffer registers, I/O ports, D Q C CCQ 1 1 O V8 bidirectional bus drivers, and working registers. 3 2 1 20 19 The eight latches of the ’LS373 and ’S373 are 2D 4 18 8D transparent D-type latches, meaning that while 2Q 5 17 7D the enable (C or CLK) input is high, the Q outputs 3Q 6 16 7Q follow the data (D) inputs. When C or CLK is taken 3D 7 15 6Q low, the output is latched at the level of the data 4D 8 14 6D that was set up. 9 10 11 12 13 The eight flip-flops of the ’LS374 and ’S374 are Q D† Q D edge-triggered D-type flip-flops. On the positive 4 N C5 5 G transition of the clock, the Q outputs are set to the †C for ’LS373 and ’S373; CLK for ’LS374 and ’S374. logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74LS373N SN74LS373N Tube SN74LS374N SN74LS374N PPDDIIPP – NN Tube SN74S373N SN74S373N Tube SN74S374N SN74S374N Tube SN74LS373DW LLSS337733 Tape and reel SN74LS373DWR Tube SN74LS374DW LLSS337744 Tape and reel SN74LS374DWR 00°°CC ttoo 7700°°CC SSOOIICC – DDWW Tube SN74S373DW SS337733 Tape and reel SN74S373DWR Tube SN74S374DW SS337744 Tape and reel SN74S374DWR Tape and reel SN74LS373NSR 74LS373 SOP – NS Tape and reel SN74LS374NSR 74LS374 Tape and reel SN74S374NSR 74S374 SSOP – DB Tape and reel SN74LS374DBR LS374A Tube SN54LS373J SN54LS373J Tube SNJ54LS373J SNJ54LS373J Tube SN54LS374J SN54LS374J Tube SNJ54LS374J SNJ54LS374J CCDDIIPP – JJ Tube SN54S373J SN54S373J Tube SNJ54S373J SNJ54S373J Tube SN54S374J SN54S374J –55°C to 125°C Tube SNJ54S374J SNJ54S374J Tube SNJ54LS373W SNJ54LS373W CFP – W Tube SNJ54LS374W SNJ54LS374W Tube SNJ54S374W SNJ54S374W Tube SNJ54LS373FK SNJ54LS373FK Tube SNJ54LS374FK SNJ54LS374FK LLCCCCCC – FFKK Tube SNJ54S373FK SNJ54S373FK Tube SNJ54S374FK SNJ54S374FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 Function Tables ’LS373, ’S373 (each latch) INPUTS OUTPUT OC C D Q L H H H L H L L L L X Q0 H X X Z ’LS374, ’S374 (each latch) INPUTS OUTPUT OC CLK D Q L ↑ H H L ↑ L L L L X Q0 H X X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 logic diagrams (positive logic) ’LS373, ’S373 ’LS374, ’S374 Transparent Latches Positive-Edge-Triggered Flip-Flops 1 1 OC OC 11 11 C CLK C1 2 C1 2 3 1Q 3 1Q 1D 1D 1D 1D C1 5 C1 5 4 2Q 4 2Q 2D 1D 2D 1D C1 6 C1 6 7 3Q 7 3Q 3D 1D 3D 1D C1 9 C1 9 8 4Q 8 4Q 4D 1D 4D 1D C1 12 C1 12 13 5Q 13 5Q 5D 1D 5D 1D C1 15 C1 15 14 6Q 14 6Q 6D 1D 6D 1D C1 16 C1 16 17 7Q 17 7Q 7D 1D 7D 1D C1 19 C1 19 18 8Q 18 8Q 8D 1D 8D 1D for ’S373 Only for ’S374 Only Pin numbers shown are for DB, DW, J, N, NS, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 schematic of inputs and outputs ’LS373 EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- AND TYPICAL OF ALL OUTPUTS OUTPUT-CONTROL INPUTS VCC VCC VCC Req = 20 kΩ NOM 17 kΩ NOM 100 Ω NOM Input Input Output ’LS374 EQUIVALENT OF DATA INPUTS EQUIVALENT OF CLOCK- AND TYPICAL OF ALL OUTPUTS OUTPUT-CONTROL INPUTS VCC VCC VCC 30 kΩ NOM 17 kΩ NOM 100 Ω NOM Input Input Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† (’LS devices) Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54LS’ SN74LS’ UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5 4.75 5 5.25 V VOH High-level output voltage 5.5 5.5 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA CLK high 15 15 ttw PPuullssee dduurraattiioonn nnss CLK low 15 15 ’LS373 5↓ 5↓ ttsu DDaattaa sseettuupp ttiimmee nnss ’LS374 20↑ 20↑ ’LS373 20↓ 20↓ tthh DDaattaa hhoolldd ttiimmee ’LS374‡ 5↑ 0↑ nnss TA Operating free-air temperature –55 125 0 70 °C ‡The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS’ SN74LS’ PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V VVOOHH HHiigghh-lleevveell oouuttppuutt vvoollttaaggee VCCCC = MIN,, VIIHH = 2 V,, 22.44 33.44 22.44 33.11 VV VIL = VIL max, IOH = MAX VVOOLL LLooww-lleevveell oouuttppuutt vvoollttaaggee VCCCC = MIN,, VIIHH = 2 V,, IOL = 12 mA 0.25 0.4 0.25 0.4 VV VIL = VIL max IOL = 24 mA 0.35 0.5 IIOOZZHH Off-state output current,, VCCCC = MAX,, VIIHH = 2 V,, 2200 2200 (cid:1)(cid:1)AA high-level voltage applied VO = 2.7 V IIOOZZLL Off-state output current,, VCCCC = MAX,, VIIHH = 2 V,, –2200 –2200 (cid:1)(cid:1)AA low-level voltage applied VO = 0.4 V Input current at maximum IIII VVCCCC == MMAAXX, VVII == 77 VV 00.11 00.11 mmAA input voltage IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 (cid:1)A IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA IOS Short-circuit output current§ VCC = MAX –30 –130 –30 –130 mA IICCCC SSuuppppllyy ccuurrrreenntt VCCCC = MAX,, ’LS373 24 40 24 40 mmAA Output control at 4.5 V ’LS374 27 40 27 40 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM TO ’LS373 ’LS374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX RL = 667 Ω(cid:0) CL = 45 pF, fmax See Note 3 35 50 MHz tPLH DDaattaa AAnnyy QQ RLL = 667 Ω(cid:0)(cid:0) CLL = 45 pF,, 12 18 nnss tPHL See Note 3 12 18 tPLH CC oorr CCLLKK AAnnyy QQ RLL = 667 Ω(cid:0)(cid:0) CLL = 45 pF,, 20 30 15 28 nnss tPHL See Note 3 18 30 19 28 tPZH OOCC AAnnyy QQ RLL = 667 Ω(cid:0)(cid:0) CLL = 45 pF,, 15 28 20 26 nnss tPZL See Note 3 25 36 21 28 ttPPHHZZ 1155 2255 1155 2288 OOCC AAnnyy QQ RRLL = 666677 ΩΩ(cid:0) CCLL = 55 ppFF nnss ttPPLLZZ 1122 2200 1122 2200 NOTE 3: Maximum clock frequency is tested with all outputs loaded. fmax = maximum clock frequency tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output tPZH= output enable time to high level tPZL = output enable time to low level tPHZ= output disable time from high level tPLZ = output disable time from low level POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 schematic of inputs and outputs ’S373 and ’S374 ’S373 and ’S374 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC 2.8 kΩ NOM 50 Ω NOM Input Output 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† (’S devices) Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W JA N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54S’ SN74S’ UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VOH High-level output voltage 5.5 5.5 V IOH High-level output current –2 –6.5 mA High 6 6 ttw PPuullssee dduurraattiioonn, cclloocckk//eennaabbllee nnss Low 7.3 7.3 ’S373 0↓ 0↓ ttsu DDaattaa sseettuupp ttiimmee nnss ’S374 5↑ 5↑ ’S373 10↓ 10↓ tthh DDaattaa hhoolldd ttiimmee nnss ’S374 2↑ 2↑ TA Operating free-air temperature –55 125 0 70 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374) PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT VIH 2 V VIL 0.8 V VIK VCC = MIN, II = –18 mA –1.2 V SN54S’ 2.4 3.4 VVOOHH VVCCCC == MMIINN, VVIIHH == 22 VV, VVIILL == 00.88 VV, IIOOHH == MMAAXX VV SN74S’ 2.4 3.1 VOL VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V IOZH VCC = MAX, VIH = 2 V, VO = 2.4 V 50 (cid:2)A IOZL VCC = MAX, VIH = 2 V, VO = 0.5 V –50 (cid:2)A II VCC = MAX, VI = 5.5 V 1 mA IIH VCC = MAX, VI = 2.7 V 50 (cid:2)A IIL VCC = MAX, VI = 0.5 V –250 (cid:2)A IOS§ VCC = MAX –40 –100 mA Outputs high 160 ’S373 Outputs low 160 Outputs disabled 190 ICC VCC = MAX Outputs high 110 mA Outputs low 140 ’’SS337744 Outputs disabled 160 CLK and OC at 4 V, D inputs at 0 V 180 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC= 5 V, TA = 25°C. §Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) FROM TO ’S373 ’S374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX RL = 280 Ω(cid:1) CL = 15 pF, fmax See Note 3 75 100 MHz tPLH DDaattaa AAnnyy QQ RLL = 280 Ω(cid:1)(cid:1)CLL = 15 pF,, 7 12 nnss tPHL See Note 3 7 12 tPLH CC oorr CCLLKK AAnnyy QQ RLL = 280 Ω(cid:1)(cid:1)CLL = 15 pF,, 7 14 8 15 nnss tPHL See Note 3 12 18 11 17 tPZH OOCC AAnnyy QQ RLL = 280 Ω(cid:1)(cid:1)CLL = 15 pF,, 8 15 8 15 nnss tPZL See Note 3 11 18 11 18 tPHZ 6 9 5 9 OOCC AAnnyy QQ RRLL == 228800 ΩΩ(cid:1)CCLL == 55 ppFF nnss tPLZ 8 12 7 12 NOTE 3. Maximum clock frequency is tested with all outputs loaded. fmax = maximum clock frequency tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output tPZH= output enable time to high level tPZL = output enable time to low level tPHZ= output disable time from high level tPLZ = output disable time from low level 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 5 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.3 V 1.3 V 1.3 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.3 V 1.3 V 1.3 V 1.3 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.3 V 1.3 V (low-level 3 V enabling) Input 1.3 V 1.3 V 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.3 V Output 1.3 V 1.3 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH – 0.5 V (see Notes C 1.3 V Output 1.3 V 1.3 V ≈1.5 V and D) (see Note D) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. H. All parameters and waveforms are not applicable to all devices . Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54S/74S DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 1 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.5 V 1.5 V 1.5 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.5 V 1.5 V 1.5 V 1.5 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.5 V 1.5 V 3 V (low-level Input 1.5 V 1.5 V enabling) 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.5 V Output 1.5 V 1.5 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH – 0.5 V Output 1.5 V 1.5 V (see Notes C 1.5 V ≈1.5 V (see Note D) VOL and D) VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. G. All parameters and waveforms are not applicable to all devices . Figure 2. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 TYPICAL APPLICATION DATA Bidirectional Bus Driver Output Control 1 1D 1Q 2D 2Q 3D 3Q ’LS374 Bidirectional 4D 4Q Bidirectional or Data Bus 1 5D 5Q Data Bus 2 ’S374 6D 6Q 7D 7Q C 8D 8Q Clock 1 Clock 2 1Q 1D 2Q C 2D 3Q 3D ’LS374 4Q 4D or 5Q 5D ’S374 6Q 6D 7Q 7D 8Q 8D Output Control 2 Clock 1 H Bus Exchange Clock Clock 2 H Clock Circuit for Bus Exchange Expandable 4-Word by 8-Bit General Register File ’LS374 or ’S374 1/2 SN74LS139 or SN74S139 G Y0 ’LS374 or ’S374 Y1 A Y2 Enable Select B Y3 ’LS374 or ’S374 ’LS374 or ’S374 1/2 SN74LS139 Y0 Y1 Y2 Y3 or SN74S139 A B G Clock Clock Select POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 78011022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78011022A SNJ54LS 374FK 7801102RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 7801102RA SNJ54LS374J 7801102SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 7801102SA SNJ54LS374W JM38510/32502B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 32502B2A JM38510/32502BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502BRA JM38510/32502BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502BSA JM38510/32502SRA ACTIVE CDIP J 20 20 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502SRA JM38510/32502SSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502SSA JM38510/32503B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 32503B2A JM38510/32503BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32503BRA JM38510/32503BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32503BSA M38510/32502B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 32502B2A M38510/32502BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502BRA M38510/32502BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502BSA M38510/32502SRA ACTIVE CDIP J 20 20 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502SRA M38510/32502SSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32502SSA M38510/32503B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 32503B2A M38510/32503BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32503BRA M38510/32503BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 32503BSA SN54LS373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54LS373J SN54LS374J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54LS374J SN54S373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54S373J SN54S374J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54S374J SN74LS373DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS373 & no Sb/Br) SN74LS373DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS373 & no Sb/Br) SN74LS373N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74LS373N (RoHS) SN74LS373NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74LS373N (RoHS) SN74LS373NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74LS373 & no Sb/Br) SN74LS374DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS374A & no Sb/Br) SN74LS374DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS374 & no Sb/Br) SN74LS374DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS374 & no Sb/Br) SN74LS374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS374 & no Sb/Br) SN74LS374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74LS374N (RoHS) SN74LS374NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74LS374N (RoHS) SN74LS374NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74LS374 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LS374NSRG4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74LS374 & no Sb/Br) SN74S373N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74S373N (RoHS) SN74S374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74S374N (RoHS) SNJ54LS373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS 373FK SNJ54LS373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54LS373J SNJ54LS373W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54LS373W SNJ54LS374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78011022A SNJ54LS 374FK SNJ54LS374J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 7801102RA SNJ54LS374J SNJ54LS374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 7801102SA SNJ54LS374W SNJ54S373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 373FK SNJ54S373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54S373J SNJ54S374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 374FK SNJ54S374J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54S374J SNJ54S374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54S374W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LS373, SN54LS373-SP, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 : •Catalog: SN74LS373, SN54LS373, SN74LS374, SN74S373, SN74S374 •Military: SN54LS373, SN54LS374, SN54S373, SN54S374 •Space: SN54LS373-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LS373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LS373NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LS374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LS374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LS374NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LS373DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LS373NSR SO NS 20 2000 367.0 367.0 45.0 SN74LS374DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LS374DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LS374NSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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