(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 ’147, ’LS147 ’148, ’LS148 (cid:1) (cid:1) Encode 10-Line Decimal to 4-Line BCD Encode 8 Data Lines to 3-Line Binary (cid:1) Applications Include: (Octal) (cid:1) − Keyboard Encoding Applications Include: − Range Selection − n-Bit Encoding − Code Converters and Generators SN54147, SN54LS147...J OR W PACKAGE SN54148, SN54LS148...J OR W PACKAGE SN74147, SN74LS147...D OR N PACKAGE SN74148, SN74LS148...D, N, OR NS PACKAGE (TOP VIEW) (TOP VIEW) 4 1 16 VCC 4 1 16 VCC 5 2 15 NC 5 2 15 E0 6 3 14 D 6 3 14 GS 7 4 13 3 7 4 13 3 8 5 12 2 EI 5 12 2 C 6 11 1 A2 6 11 1 B 7 10 9 A1 7 10 0 GND 8 9 A GND 8 9 A0 SN54LS147...FK PACKAGE SN54LS148...FK PACKAGE (TOP VIEW) (TOP VIEW) C C C CC C C0 5 4 NV N 5 4 NV E 3 2 1 20 19 3 2 1 20 19 6 4 18 D 6 4 18 GS 7 5 17 3 7 5 17 3 NC 6 16 NC NC 6 16 NC 8 7 15 2 EI 7 15 2 C 8 14 1 A2 8 14 1 9 10 1112 13 9 10 1112 13 BD C A 9 1 DC 0 0 N N A NN A G G NC − No internal connection TYPICAL TYPICAL TYPE DATA POWER DELAY DISSIPATION ’147 10 ns 225 mW ’148 10 ns 190 mW ’LS147 15 ns 60 mW ’LS148 15 ns 60 mW NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:23)(cid:24)(cid:19)(cid:21)(cid:27)(cid:26)(cid:11)(cid:12)(cid:19)(cid:2) (cid:21)(cid:20)(cid:11)(cid:20) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$(- Copyright  2004, Texas Instruments Incorporated (cid:23)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $.( $(!"% (cid:31)(cid:30) (cid:11)(/#% (cid:12)(cid:29)%$!’"((cid:29)$% (cid:19)(cid:29) )!(cid:31),’&$% &(cid:31)")+(cid:28)#(cid:29)$ $(cid:31) (cid:13)(cid:12)(cid:9)(cid:17)(cid:23)(cid:24)3(cid:17)(cid:22)(cid:8)(cid:3)(cid:22)(cid:3)(cid:7) #++ )#!#"($(!% #!( $(%$(, %$#(cid:29),#!, 0#!!#(cid:29)$1- (cid:23)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( ’(cid:29)+(%% (cid:31)$.(!0(cid:28)%( (cid:29)(cid:31)$(,- (cid:19)(cid:29) #++ (cid:31)$.(! )!(cid:31),’&$%(cid:7) )!(cid:31),’&$(cid:28)(cid:31)(cid:29) $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 description/ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube SN74LS148N SN74LS148N Tube SN74LS148D 00°°CC ttoo 7700°°CC SSOOIICC −− DD LLSS114488 Tape and reel SN74LS148DR SOP − NS Tape and reel SN74LS148NSR 74LS148 CDIP − J Tube SNJ54LS148J SNJ54LS148J −−5555°CC ttoo 112255°CC CFP − W Tube SNJ54LS148W SNJ54LS148W LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE − ’147, ’LS147 INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 D C B A H H H H H H H H H H H H H X X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L X L H H H H H H H H H L H L H H H H H H H H H H H L H = high logic level, L = low logic level, X = irrelevant 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 FUNCTION TABLE − ’148, ’LS148 INPUTS OUTPUTS EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H H = high logic level, L = low logic level, X = irrelevant POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 ’147, ’LS147 logic diagram (positive logic) (11) 1 (12) 2 (9) A (13) 3 (1) 4 (7) B (2) 5 (3) 6 7 (4) (6) C (5) 8 (14) (10) D 9 Pin numbers shown are for D, J, N, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 ’148, ’LS148 logic diagram (positive logic) (10) 0 (15) EO (14) (11) G5 1 (12) 2 (9) A0 (13) 3 (1) 4 (7) A1 (2) 5 (3) 6 (4) (6) 7 A2 (5) EI Pin numbers shown are for D, J, N, NS, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 schematics of inputs and outputs ’147, ’148 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC (cid:1)(cid:2) Ω NOM Req Input Output 0 input (’148): Req = 2 kΩ NOM All other inputs: Req = 4 kΩ NOM ’LS147, ’LS148 TYPICAL OF ALL OUTPUTS EQUIVALENT OF ALL INPUTS VCC VCC 120 Ω NOM Req Input Output ’LS148 inputs 1–7: Req = 9 kΩ NOM All other inputs: Req = 18 kΩ NOM 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V: ’147, ’148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I ’LS147, ’LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the eight data lines, 0 through 7. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54’ SN74’ SN54LS’ SN74LS’ UUNNIITT MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current −800 −800 −400 −400 µA IOL Low-level output current 16 16 4 8 mA TA Operating free-air temperature −55 125 0 70 −55 125 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ’147 ’148 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VIK Input clamp voltage VCC = MIN, II = −12 mA −1.5 −1.5 V VCC = MIN, VIH = 2 V, VOH High-level output voltage VIL = 0.8 V, IOH = −800 µA 2.4 3.3 2.4 3.3 V VCC = MIN, VIH = 2 V, VOL Low-level output voltage VIL = 0.8 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V Input current at maximum input II voltage VCC = MIN, VI = 5.5 V 1 1 mA HHiigghh--lleevveell iinnppuutt 0 input 40 IIIIHH current Any input except 0 VVCCCC == MMAAXX,, VVII == 22..44 VV 40 80 µAA LLooww--lleevveell iinnppuutt 0 input −1.6 IIIILL current Any input except 0 VVCCCC == MMAAXX,, VVII == 00..44 VV −1.6 −3.2 mmAA IOS Short-circuit output current§ VCC = MAX −35 −85 −35 −85 mA IICCCC SSuuppppllyy ccuurrrreenntt VVCCCC == MMAAXX Condition 1 50 70 40 60 mmAA (See Note 5) Condition 2 42 62 35 55 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. NOTE 5: For ’147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. SN54147, SN74147 switching characteristics, V = 5 V, T = 25(cid:1)C (see Figure 1) CC A FROM TO TEST PARAMETER WAVEFORM MIN TYP MAX UNIT (INPUT) (OUTPUT) CONDITIONS tPLH 9 14 AAnnyy AAnnyy IInn--pphhaassee oouuttppuutt nnss tPHL CCLL == 1155 ppFF,, 7 11 tPLH RRLL == 440000 Ω 13 19 AAnnyy AAnnyy OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 12 19 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 SN54148, SN74148 switching characteristics, V = 5 V, T = 25(cid:1)C (see Figure 1) CC A FROM TO TEST PARAMETER† WAVEFORM MIN TYP MAX UNIT (INPUT) (OUTPUT) CONDITIONS tPLH 10 15 11––77 AA00,, AA11,, oorr AA22 IInn--pphhaassee oouuttppuutt nnss tPHL 9 14 tPLH 13 19 11––77 AA00,, AA11,, oorr AA22 OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 12 19 tPLH 6 10 00––77 EEOO OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 14 25 tPLH CCLL == 1155 ppFF,, 18 30 tPHL 00––77 GGSS IInn--pphhaassee oouuttppuutt RRLL == 440000 Ω 14 25 nnss tPLH 10 15 EEII AA00,, AA11,, oorr AA22 IInn--pphhaassee oouuttppuutt nnss tPHL 10 15 tPLH 8 12 EEII GGSS IInn--pphhaassee oouuttppuutt nnss tPHL 10 15 tPLH 10 15 EEII EEOO IInn--pphhaassee oouuttppuutt nnss tPHL 17 30 †tPLH = propagation delay time, low-to-high-level output. tPHL = propagation delay time, high-to-low-level output. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS’ SN74LS’ PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VIK Input clamp voltage VCC = MIN, II = −18 mA −1.5 −1.5 V VCC = MIN, VIH = 2 V, VOH High-level output voltage VIL = 0.8 V, IOH = −400 µA 2.5 3.4 2.7 3.4 V VCCCC = MIN, IOL = 4 mA 0.25 0.4 0.25 0.4 VVOOLL LLooww--lleevveell oouuttppuutt vvoollttaaggee VVIIHH == 22 VV,, VV VIL = VIL MAX IOL = 8 mA 0.35 0.5 Input current at ’LS148 inputs 1–7 0.2 0.2 IIII mmaaxxiimmuumm iinnppuutt VVCCCC == MMAAXX,, VVII == 77 VV mmAA voltage All other inputs 0.1 0.1 HHiigghh--lleevveell iinnppuutt ’LS148 inputs 1–7 40 40 IIIIHH current All other inputs VVCCCC == MMAAXX,, VVII == 22..77 VV 20 20 µAA LLooww--lleevveell iinnppuutt ’LS148 inputs 1–7 −0.8 −0.8 IIIILL current All other inputs VVCCCC == MMAAXX,, VVII == 00..44 VV −0.4 −0.4 mmAA IOS Short-circuit output current§ VCC = MAX −20 −100 −20 −100 mA IICCCC SSuuppppllyy ccuurrrreenntt VVCCCC == MMAAXX Condition 1 12 20 12 20 mmAA (See Note 6) Condition 2 10 17 10 17 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. NOTE 6: For ’LS147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 SN54LS147, SN74LS147 switching characteristics, V = 5 V, T = 25(cid:1)C (see Figure 2) CC A FROM TO TEST PARAMETER WAVEFORM MIN TYP MAX UNIT (INPUT) (OUTPUT) CONDITIONS tPLH 12 18 AAnnyy AAnnyy IInn--pphhaassee oouuttppuutt nnss tPHL CCLL == 1155 ppFF,, 12 18 tPLH RRLL == 22 kkΩ 21 33 AAnnyy AAnnyy OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 15 23 SN54LS148, SN74LS148 switching characteristics, V = 5 V, T = 25(cid:1)C (see Figure 2) CC A FROM TO TEST PARAMETER† WAVEFORM MIN TYP MAX UNIT (INPUT) (OUTPUT) CONDITIONS tPLH 14 18 11––77 AA00,, AA11,, oorr AA22 IInn--pphhaassee oouuttppuutt nnss tPHL 15 25 tPLH 20 36 11––77 AA00,, AA11,, oorr AA22 OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 16 29 tPLH 7 18 00––77 EEOO OOuutt--ooff--pphhaassee oouuttppuutt nnss tPHL 25 40 tPLH CCLL == 1155 ppFF,, 35 55 tPHL 00––77 GGSS IInn--pphhaassee oouuttppuutt RRLL == 22 kkΩ 9 21 nnss tPLH 16 25 EEII AA00,, AA11,, oorr AA22 IInn--pphhaassee oouuttppuutt nnss tPHL 12 25 tPLH 12 17 EEII GGSS IInn--pphhaassee oouuttppuutt nnss tPHL 14 36 tPLH 12 21 EEII EEOO IInn--pphhaassee oouuttppuutt nnss tPHL 23 35 †tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 1 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.5 V 1.5 V 1.5 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.5 V 1.5 V 1.5 V 1.5 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.5 V 1.5 V 3 V (low-level Input 1.5 V 1.5 V enabling) 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.5 V Output 1.5 V 1.5 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH − 0.5 V Output 1.5 V 1.5 V (see Notes C 1.5 V ≈1.5 V (see Note D) VOL and D) VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 5 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.3 V 1.3 V 1.3 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.3 V 1.3 V 1.3 V 1.3 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.3 V 1.3 V (low-level 3 V enabling) Input 1.3 V 1.3 V 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.3 V Output 1.3 V 1.3 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH − 0.5 V (see Notes C 1.3 V Output 1.3 V 1.3 V ≈1.5 V and D) (see Note D) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4)(cid:8) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:6)(cid:16)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:6)(cid:7) (cid:1)(cid:2)(cid:6)(cid:4)(cid:9)(cid:1)(cid:5)(cid:4)(cid:8) (cid:5)(cid:15)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:4)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:20)(cid:2)(cid:21) (cid:8)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:11)(cid:19) (cid:22)(cid:17)(cid:9)(cid:12)(cid:2)(cid:18) (cid:23)(cid:24)(cid:12)(cid:19)(cid:24)(cid:12)(cid:11)(cid:25) (cid:18)(cid:2)(cid:26)(cid:19)(cid:21)(cid:18)(cid:24)(cid:1) SDLS053B − OCTOBER 1976 − REVISED MAY 2004 APPLICATION INFORMATION 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415 Enable (active low) 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI ’148/’LS148 ’148/LS148 EO A0 A1 A2 GS EO A0 A1 A2 GS ’08/’LS08 0 1 2 3 Priority Flag (active low) Encoded Data (active low) 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415 Enable (active low) 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI ’148/’LS148 ’148/’LS148 EO A0 A1 A2 GS EO A0 A1 A2 GS ’HC00 0 1 2 3 Priority Flag (active high) Encoded Data (active high) Figure 3. Priority Encoder for 16 Bits Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be considered when strobing the outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 78027012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK 7802701EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J 7802701FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W JM38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 36001B2A JM38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BEA JM38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BFA M38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 36001B2A M38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BEA M38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BFA SN54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS148J SN74LS148D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 & no Sb/Br) SN74LS148DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 & no Sb/Br) SN74LS148N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N & no Sb/Br) SN74LS148NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS148 & no Sb/Br) SNJ54LS148FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK SNJ54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ54LS148W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LS148, SN74LS148 : •Catalog: SN74LS148 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 •Military: SN54LS148 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LS148DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LS148DR SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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