(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13) (cid:10)(cid:14)(cid:7)(cid:15)(cid:16)(cid:17) (cid:16)(cid:18)(cid:1)(cid:19)(cid:7)(cid:19)(cid:20)(cid:17)(cid:14)(cid:17)(cid:10)(cid:21)(cid:17)(cid:14)(cid:7)(cid:22)(cid:19)(cid:21)(cid:21)(cid:17)(cid:22)(cid:17)(cid:10) (cid:23)(cid:13)(cid:19)(cid:16)(cid:14)(cid:23)(cid:13)(cid:18)(cid:16)(cid:1) (cid:24)(cid:19)(cid:7)(cid:5) (cid:6)(cid:13)(cid:17)(cid:12)(cid:22) (cid:12)(cid:2)(cid:10) (cid:16)(cid:22)(cid:17)(cid:1)(cid:17)(cid:7) SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 (cid:1) Operating Voltage Range of 4.5 V to 5.5 V SN54HCT74...J OR W PACKAGE (cid:1) SN74HCT74...D, DB, N, NS, OR PW PACKAGE Outputs Can Drive Up To 10 LSTTL Loads (TOP VIEW) (cid:1) Low Power Consumption, 40-µA Max I CC (cid:1) Typical tpd = 17 ns 1CLR 1 14 VCC (cid:1) ±4-mA Output Drive at 5 V 1D 2 13 2CLR (cid:1) Low Input Current of 1 µA Max 1CLK 3 12 2D 1PRE 4 11 2CLK (cid:1) Inputs Are TTL-Voltage Compatible 1Q 5 10 2PRE 1Q 6 9 2Q description/ordering information GND 7 8 2Q The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low SN54HCT74...FK PACKAGE level at the preset (PRE) or clear (CLR) inputs sets (TOP VIEW) or resets the outputs, regardless of the levels of R R L CL the other inputs. When PRE and CLR are inactive D C C CC 1 1 N V 2 (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs 3 2 1 20 19 on the positive-going edge of the clock (CLK) 1CLK 4 18 2D pulse. Clock triggering occurs at a voltage level NC 5 17 NC and is not directly related to the rise time of CLK. 1PRE 6 16 2CLK Following the hold-time interval, data at the NC 7 15 NC D input may be changed without affecting the 1Q 8 14 2PRE 9 10 1112 13 levels at the outputs. QD C QQ 1N N 22 G NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HCT74N SN74HCT74N Tube of 50 SN74HCT74D SSOOIICC −− DD Reel of 2500 SN74HCT74DR HHCCTT7744 Reel of 250 SN74HCT74DT −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HCT74NSR HCT74 SSOP − DB Reel of 2000 SN74HCT74DBR HT74 Tube of 90 SN74HCT74PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HCT74PWR HHTT7744 Reel of 250 SN74HCT74PWT CDIP − J Tube of 25 SNJ54HCT74J SNJ54HCT74J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HCT74W SNJ54HCT74W LCCC − FK Tube of 55 SNJ54HCT74FK SNJ54HCT74FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:11)(cid:2)(cid:13)(cid:17)(cid:1)(cid:1) (cid:18)(cid:7)(cid:5)(cid:17)(cid:22)(cid:24)(cid:19)(cid:1)(cid:17) (cid:2)(cid:18)(cid:7)(cid:17)(cid:10) (cid:25)(cid:26)(cid:27)(cid:28) (cid:29)(cid:30)(cid:31)!"#$(cid:25) (cid:31)(cid:30)$(cid:25)%(cid:27)$(cid:28) (cid:16)(cid:22)(cid:18)(cid:10)(cid:11)(cid:6)(cid:7)(cid:19)(cid:18)(cid:2) Copyright  2004, Texas Instruments Incorporated (cid:10)(cid:12)(cid:7)(cid:12) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)!’’#$(cid:25) %(cid:28) (cid:30)& (!)*(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$ (cid:29)%(cid:25)#+ (cid:16)’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:31)(cid:30)$&(cid:30)’" (cid:25)(cid:30) (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) (#’ (cid:25)(cid:26)# (cid:25)#’"(cid:28) (cid:30)& (cid:7)#,%(cid:28) (cid:19)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) (cid:28)(cid:25)%$(cid:29)%’(cid:29) -%’’%$(cid:25).+ (cid:16)’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:27)(cid:30)$ (’(cid:30)(cid:31)#(cid:28)(cid:28)(cid:27)$/ (cid:29)(cid:30)#(cid:28) $(cid:30)(cid:25) $#(cid:31)#(cid:28)(cid:28)%’(cid:27)*. (cid:27)$(cid:31)*!(cid:29)# (cid:25)#(cid:28)(cid:25)(cid:27)$/ (cid:30)& %** (%’%"#(cid:25)#’(cid:28)+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13) (cid:10)(cid:14)(cid:7)(cid:15)(cid:16)(cid:17) (cid:16)(cid:18)(cid:1)(cid:19)(cid:7)(cid:19)(cid:20)(cid:17)(cid:14)(cid:17)(cid:10)(cid:21)(cid:17)(cid:14)(cid:7)(cid:22)(cid:19)(cid:21)(cid:21)(cid:17)(cid:22)(cid:17)(cid:10) (cid:23)(cid:13)(cid:19)(cid:16)(cid:14)(cid:23)(cid:13)(cid:18)(cid:16)(cid:1) (cid:24)(cid:19)(cid:7)(cid:5) (cid:6)(cid:13)(cid:17)(cid:12)(cid:22) (cid:12)(cid:2)(cid:10) (cid:16)(cid:22)(cid:17)(cid:1)(cid:17)(cid:7) SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H (cid:1) H H L H H (cid:1) L L H H H L X Q0 Q0 †This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic diagram (positive logic) PRE C CLK C Q C TG C C C C D TG TG TG Q C C C CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13) (cid:10)(cid:14)(cid:7)(cid:15)(cid:16)(cid:17) (cid:16)(cid:18)(cid:1)(cid:19)(cid:7)(cid:19)(cid:20)(cid:17)(cid:14)(cid:17)(cid:10)(cid:21)(cid:17)(cid:14)(cid:7)(cid:22)(cid:19)(cid:21)(cid:21)(cid:17)(cid:22)(cid:17)(cid:10) (cid:23)(cid:13)(cid:19)(cid:16)(cid:14)(cid:23)(cid:13)(cid:18)(cid:16)(cid:1) (cid:24)(cid:19)(cid:7)(cid:5) (cid:6)(cid:13)(cid:17)(cid:12)(cid:22) (cid:12)(cid:2)(cid:10) (cid:16)(cid:22)(cid:17)(cid:1)(cid:17)(cid:7) SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 recommended operating conditions (see Note 3) SN54HCT74 SN74HCT74 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V ∆t/∆v Input transition rise/fall time 500 500 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT74 SN74HCT74 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −20 µA 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44..55 VV VV IOH = −4 mA 3.98 4.3 3.7 3.84 IOL = 20 µA 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44..55 VV VV IOL = 4 mA 0.17 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 5.5 V 4 80 40 µA One input at 0.5 V or 2.4 V, ∆ICC† Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA 4.5 V Ci to 5.5 V 3 10 10 10 pF †This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT74 SN74HCT74 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 4.5 V 27 18 22 ffcclloocckk CClloocckk ffrreeqquueennccyy MMHHzz 5.5 V 30 20 24 4.5 V 16 24 20 PPRREE oorr CCLLRR llooww 5.5 V 14 21 18 ttww PPuullssee dduurraattiioonn nnss 4.5 V 18 27 23 CCLLKK hhiigghh oorr llooww 5.5 V 16 24 21 4.5 V 12 18 15 DDaattaa 5.5 V 11 16 14 ttssuu SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss 4.5 V 0 0 0 PPRREE oorr CCLLRR iinnaaccttiivvee 5.5 V 0 0 0 4.5 V 0 0 0 tthh HHoolldd ttiimmee,, ddaattaa aafftteerr CCLLKK↑↑ nnss 5.5 V 0 0 0 (cid:16)(cid:22)(cid:18)(cid:10)(cid:11)(cid:6)(cid:7) (cid:16)(cid:22)(cid:17)(cid:20)(cid:19)(cid:17)(cid:24) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)(cid:30)$(cid:31)#’$(cid:28) (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:27)$ (cid:25)(cid:26)# &(cid:30)’"%(cid:25)(cid:27)0# (cid:30)’ (cid:29)#(cid:28)(cid:27)/$ ((cid:26)%(cid:28)# (cid:30)& (cid:29)#0#*(cid:30)("#$(cid:25)+ (cid:6)(cid:26)%’%(cid:31)(cid:25)#’(cid:27)(cid:28)(cid:25)(cid:27)(cid:31) (cid:29)%(cid:25)% %$(cid:29) (cid:30)(cid:25)(cid:26)#’ (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) %’# (cid:29)#(cid:28)(cid:27)/$ /(cid:30)%*(cid:28)+ (cid:7)#,%(cid:28) (cid:19)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) ’#(cid:28)#’0#(cid:28) (cid:25)(cid:26)# ’(cid:27)/(cid:26)(cid:25) (cid:25)(cid:30) (cid:31)(cid:26)%$/# (cid:30)’ (cid:29)(cid:27)(cid:28)(cid:31)(cid:30)$(cid:25)(cid:27)$!# (cid:25)(cid:26)#(cid:28)# (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) -(cid:27)(cid:25)(cid:26)(cid:30)!(cid:25) $(cid:30)(cid:25)(cid:27)(cid:31)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13) (cid:10)(cid:14)(cid:7)(cid:15)(cid:16)(cid:17) (cid:16)(cid:18)(cid:1)(cid:19)(cid:7)(cid:19)(cid:20)(cid:17)(cid:14)(cid:17)(cid:10)(cid:21)(cid:17)(cid:14)(cid:7)(cid:22)(cid:19)(cid:21)(cid:21)(cid:17)(cid:22)(cid:17)(cid:10) (cid:23)(cid:13)(cid:19)(cid:16)(cid:14)(cid:23)(cid:13)(cid:18)(cid:16)(cid:1) (cid:24)(cid:19)(cid:7)(cid:5) (cid:6)(cid:13)(cid:17)(cid:12)(cid:22) (cid:12)(cid:2)(cid:10) (cid:16)(cid:22)(cid:17)(cid:1)(cid:17)(cid:7) SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HCT74 SN74HCT74 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 4.5 V 27 40 18 22 ffmmaaxx MMHHzz 5.5 V 30 46 20 24 4.5 V 21 35 53 44 PPRREE oorr CCLLRR QQ oorr QQ 5.5 V 17 31 48 40 ttppdd nnss 4.5 V 20 28 42 35 CCLLKK QQ oorr QQ 5.5 V 18 25 38 31 4.5 V 8 15 22 19 tttt QQ oorr QQ nnss 5.5 V 7 14 20 17 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per flip-flop No load 35 pF PARAMETER MEASUREMENT INFORMATION From Output Test High-Level 3 V Under Test Point Pulse 1.3 V 1.3 V 0 V CL = 50 pF (see Note A) tw 3 V Low-Level LOAD CIRCUIT Pulse 1.3 V 1.3 V 0 V 3 V VOLTAGE WAVEFORMS Input 1.3 V 1.3 V PULSE DURATIONS 0 V tPLH tPHL In-Phase VOH Reference 3 V 90% 90% 1.3 V Output 1.3 V 1.3 V Input 10% 10% VOL 0 V tr tf tsu th tPHL tPLH Out-of- VOH Data 2.7 V 2.7 V 3 V Phase 90% 1.3 V 1.3 V 90% Input 1.3 V 1.3 V 0.3 V 0.3 V Output 10% 10% 0 V VOL tf tr tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES SETUP AND HOLD AND INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms (cid:16)(cid:22)(cid:18)(cid:10)(cid:11)(cid:6)(cid:7) (cid:16)(cid:22)(cid:17)(cid:20)(cid:19)(cid:17)(cid:24) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)(cid:30)$(cid:31)#’$(cid:28) (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:27)$ (cid:25)(cid:26)# &(cid:30)’"%(cid:25)(cid:27)0# (cid:30)’ (cid:29)#(cid:28)(cid:27)/$ ((cid:26)%(cid:28)# (cid:30)& (cid:29)#0#*(cid:30)("#$(cid:25)+ (cid:6)(cid:26)%’%(cid:31)(cid:25)#’(cid:27)(cid:28)(cid:25)(cid:27)(cid:31) (cid:29)%(cid:25)% %$(cid:29) (cid:30)(cid:25)(cid:26)#’ (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) %’# (cid:29)#(cid:28)(cid:27)/$ /(cid:30)%*(cid:28)+ (cid:7)#,%(cid:28) (cid:19)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) ’#(cid:28)#’0#(cid:28) (cid:25)(cid:26)# ’(cid:27)/(cid:26)(cid:25) (cid:25)(cid:30) (cid:31)(cid:26)%$/# (cid:30)’ (cid:29)(cid:27)(cid:28)(cid:31)(cid:30)$(cid:25)(cid:27)$!# (cid:25)(cid:26)#(cid:28)# (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) -(cid:27)(cid:25)(cid:26)(cid:30)!(cid:25) $(cid:30)(cid:25)(cid:27)(cid:31)#+ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) JM38510/65352B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65352B2A JM38510/65352BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65352BCA JM38510/65352BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65352BDA M38510/65352B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65352B2A M38510/65352BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65352BCA M38510/65352BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65352BDA SN74HCT74D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT74 & no Sb/Br) SN74HCT74DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HCT74N & no Sb/Br) SN74HCT74NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HCT74N & no Sb/Br) SN74HCT74NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT74 & no Sb/Br) SN74HCT74PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT74 & no Sb/Br) SN74HCT74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT74 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HCT74PWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT74 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HCT74, SN74HCT74 : •Catalog: SN74HCT74 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Military: SN54HCT74 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HCT74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HCT74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HCT74NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HCT74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HCT74PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HCT74DR SOIC D 14 2500 367.0 367.0 38.0 SN74HCT74DT SOIC D 14 250 210.0 185.0 35.0 SN74HCT74NSR SO NS 14 2000 367.0 367.0 38.0 SN74HCT74PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HCT74PWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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