(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:19) (cid:20)(cid:14)(cid:21)(cid:18)(cid:16)(cid:20)(cid:14)(cid:12)(cid:18)(cid:1) (cid:22)(cid:21)(cid:7)(cid:5) (cid:6)(cid:14)(cid:19)(cid:13)(cid:23) SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 (cid:1) (cid:1) Operating Voltage Range of 4.5 V to 5.5 V Inputs Are TTL-Voltage Compatible (cid:1) (cid:1) Outputs Can Drive Up To 10 LSTTL Loads Contain Eight D-Type Flip-Flops (cid:1) Low Power Consumption, 80-µA Max I (cid:1) Direct Clear Input CC (cid:1) (cid:1) Typical tpd = 12 ns Applications Include: (cid:1) ±4-mA Output Drive at 5 V − Buffer/Storage Registers (cid:1) Low Input Current of 1 µA Max − Shift Registers − Pattern Generators SN54HCT273...J OR W PACKAGE SN54HCT273...FK PACKAGE SN74HCT273...DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) R C D Q L CQ CLR 1 20 V 1 1 CV 8 CC 1Q 2 19 8Q 3 2 1 20 19 1D 3 18 8D 2D 4 18 8D 2D 4 17 7D 2Q 5 17 7D 2Q 5 16 7Q 3Q 6 16 7Q 3Q 6 15 6Q 3D 7 15 6Q 3D 7 14 6D 4D 8 14 6D 9 10 11 1213 4D 8 13 5D 4Q 9 12 5Q Q D K Q D 4 N L 5 5 GND 10 11 CLK G C description/ordering information These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLR. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 20 SN74HCT273N SN74HCT273N Tube of 25 SN74HCT273DW SSOOIICC −− DDWW HHCCTT227733 Reel of 2000 SN74HCT273DWR SOP − NS Reel of 2000 SN74HCT273NSR HCT273 −−4400°°CC ttoo 8855°°CC SSOP − DB Reel of 2000 SN74HCT273DBR HT273 Tube of 70 SN74HCT273PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HCT273PWR HHTT227733 Reel of 250 SN74HCT273PWT CDIP − J Tube of 20 SNJ54HCT273J SNJ54HCT273J −−5555°CC ttoo 112255°CC CFP − W Tube of 85 SNJ54HCT273W SNJ54HCT273W LCCC − FK Tube of 55 SNJ54HCT273FK SNJ54HCT273FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:24)(cid:2)(cid:14)(cid:19)(cid:1)(cid:1) (cid:12)(cid:7)(cid:5)(cid:19)(cid:23)(cid:22)(cid:21)(cid:1)(cid:19) (cid:2)(cid:12)(cid:7)(cid:19)(cid:15) (cid:25)(cid:26)(cid:27)(cid:28) (cid:29)(cid:30)(cid:31)!"#$(cid:25) (cid:31)(cid:30)$(cid:25)%(cid:27)$(cid:28) (cid:18)(cid:23)(cid:12)(cid:15)(cid:24)(cid:6)(cid:7)(cid:21)(cid:12)(cid:2) Copyright  2003, Texas Instruments Incorporated (cid:15)(cid:13)(cid:7)(cid:13) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)!’’#$(cid:25) %(cid:28) (cid:30)& (!)*(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$ (cid:29)%(cid:25)#+ (cid:18)’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:31)(cid:30)$&(cid:30)’" (cid:25)(cid:30) (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) (#’ (cid:25)(cid:26)# (cid:25)#’"(cid:28) (cid:30)& (cid:7)#,%(cid:28) (cid:21)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) (cid:28)(cid:25)%$(cid:29)%’(cid:29) -%’’%$(cid:25).+ (cid:18)’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:27)(cid:30)$ (’(cid:30)(cid:31)#(cid:28)(cid:28)(cid:27)$/ (cid:29)(cid:30)#(cid:28) $(cid:30)(cid:25) $#(cid:31)#(cid:28)(cid:28)%’(cid:27)*. (cid:27)$(cid:31)*!(cid:29)# (cid:25)#(cid:28)(cid:25)(cid:27)$/ (cid:30)& %** (%’%"#(cid:25)#’(cid:28)+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:19) (cid:20)(cid:14)(cid:21)(cid:18)(cid:16)(cid:20)(cid:14)(cid:12)(cid:18)(cid:1) (cid:22)(cid:21)(cid:7)(cid:5) (cid:6)(cid:14)(cid:19)(cid:13)(cid:23) SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT CLR CLK D Q L X X L H ↑ H H H ↑ L L H L X Q0 logic diagram (positive logic) 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 11 CLK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q logic diagram, each flip-flop (positive logic) C C D TG TG Q C C C C TG CLK(I) C TG C C C R 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:19) (cid:20)(cid:14)(cid:21)(cid:18)(cid:16)(cid:20)(cid:14)(cid:12)(cid:18)(cid:1) (cid:22)(cid:21)(cid:7)(cid:5) (cid:6)(cid:14)(cid:19)(cid:13)(cid:23) SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT273 SN74HCT273 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V ∆t/∆v Input transition rise/fall time 500 500 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT273 SN74HCT273 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL VV IOH = −4 mA 4.5 V 3.98 4.30 3.7 3.84 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V, ∆ICC‡ Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA 4.5 V Ci to 5.5 V 3 10 10 10 pF ‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. (cid:18)(cid:23)(cid:12)(cid:15)(cid:24)(cid:6)(cid:7) (cid:18)(cid:23)(cid:19)0(cid:21)(cid:19)(cid:22) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)(cid:30)$(cid:31)#’$(cid:28) (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:27)$ (cid:25)(cid:26)# &(cid:30)’"%(cid:25)(cid:27)1# (cid:30)’ (cid:29)#(cid:28)(cid:27)/$ ((cid:26)%(cid:28)# (cid:30)& (cid:29)#1#*(cid:30)("#$(cid:25)+ (cid:6)(cid:26)%’%(cid:31)(cid:25)#’(cid:27)(cid:28)(cid:25)(cid:27)(cid:31) (cid:29)%(cid:25)% %$(cid:29) (cid:30)(cid:25)(cid:26)#’ (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) %’# (cid:29)#(cid:28)(cid:27)/$ /(cid:30)%*(cid:28)+ (cid:7)#,%(cid:28) (cid:21)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) ’#(cid:28)#’1#(cid:28) (cid:25)(cid:26)# ’(cid:27)/(cid:26)(cid:25) (cid:25)(cid:30) (cid:31)(cid:26)%$/# (cid:30)’ (cid:29)(cid:27)(cid:28)(cid:31)(cid:30)$(cid:25)(cid:27)$!# (cid:25)(cid:26)#(cid:28)# (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) -(cid:27)(cid:25)(cid:26)(cid:30)!(cid:25) $(cid:30)(cid:25)(cid:27)(cid:31)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:19) (cid:20)(cid:14)(cid:21)(cid:18)(cid:16)(cid:20)(cid:14)(cid:12)(cid:18)(cid:1) (cid:22)(cid:21)(cid:7)(cid:5) (cid:6)(cid:14)(cid:19)(cid:13)(cid:23) SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT273 SN74HCT273 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 4.5 V 25 16 20 ffcclloocckk CClloocckk ffrreeqquueennccyy MMHHzz 5.5 V 28 19 23 4.5 V 20 30 25 CCLLKK hhiigghh oorr llooww 5.5 V 18 25 22 ttww PPuullssee dduurraattiioonn nnss 4.5 V 16 24 20 CCLLRR llooww 5.5 V 14 20 17 4.5 V 20 30 25 DDaattaa 5.5 V 17 25 21 ttssuu SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss 4.5 V 20 30 25 CCLLRR iinnaaccttiivvee 5.5 V 17 25 21 4.5 V 0 0 0 tthh HHoolldd ttiimmee ddaattaa aafftteerr CCLLKK↑↑ nnss 5.5 V 0 0 0 switching characteristics over recommended operating free-air temperature range, V = 5 V ±0.5 V, CC C = 50 pF (unless otherwise noted) (see Figure 1) L SN54HCT273 FFRROOMM TTOO PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) VVCCCC TA = 25°C MMIINN MMAAXX UUNNIITT MIN TYP MAX 4.5 V 25 31 16 ffmmaaxx MMHHzz 5.5 V 28 37 19 4.5 V 15 34 50 ttppdd CCLLRR AAnnyy nnss 5.5 V 12 29 42 4.5 V 17 15 50 ttPPHHLL CCLLRR AAnnyy nnss 5.5 V 15 34 42 4.5 V 8 18 22 tttt AAnnyy nnss 5.5 V 7 19 21 switching characteristics over recommended operating free-air temperature range, V = 5 V ±0.5 V, CC C = 50 pF (unless otherwise noted) (see Figure 1) L SN74HCT273 FFRROOMM TTOO PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) VVCCCC TA = 25°C MMIINN MMAAXX UUNNIITT MIN TYP MAX 4.5 V 25 31 20 ffmmaaxx MMHHzz 5.5 V 28 37 23 4.5 V 15 34 42 ttppdd CCLLRR AAnnyy nnss 5.5 V 12 29 36 4.5 V 17 34 42 ttPPHHLL CCLLRR AAnnyy nnss 5.5 V 15 29 36 4.5 V 8 15 19 tttt AAnnyy nnss 5.5 V 7 14 17 (cid:18)(cid:23)(cid:12)(cid:15)(cid:24)(cid:6)(cid:7) (cid:18)(cid:23)(cid:19)0(cid:21)(cid:19)(cid:22) (cid:27)$&(cid:30)’"%(cid:25)(cid:27)(cid:30)$ (cid:31)(cid:30)$(cid:31)#’$(cid:28) (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) (cid:27)$ (cid:25)(cid:26)# &(cid:30)’"%(cid:25)(cid:27)1# (cid:30)’ (cid:29)#(cid:28)(cid:27)/$ ((cid:26)%(cid:28)# (cid:30)& (cid:29)#1#*(cid:30)("#$(cid:25)+ (cid:6)(cid:26)%’%(cid:31)(cid:25)#’(cid:27)(cid:28)(cid:25)(cid:27)(cid:31) (cid:29)%(cid:25)% %$(cid:29) (cid:30)(cid:25)(cid:26)#’ (cid:28)(#(cid:31)(cid:27)&(cid:27)(cid:31)%(cid:25)(cid:27)(cid:30)$(cid:28) %’# (cid:29)#(cid:28)(cid:27)/$ /(cid:30)%*(cid:28)+ (cid:7)#,%(cid:28) (cid:21)$(cid:28)(cid:25)’!"#$(cid:25)(cid:28) ’#(cid:28)#’1#(cid:28) (cid:25)(cid:26)# ’(cid:27)/(cid:26)(cid:25) (cid:25)(cid:30) (cid:31)(cid:26)%$/# (cid:30)’ (cid:29)(cid:27)(cid:28)(cid:31)(cid:30)$(cid:25)(cid:27)$!# (cid:25)(cid:26)#(cid:28)# (’(cid:30)(cid:29)!(cid:31)(cid:25)(cid:28) -(cid:27)(cid:25)(cid:26)(cid:30)!(cid:25) $(cid:30)(cid:25)(cid:27)(cid:31)#+ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:19) (cid:20)(cid:14)(cid:21)(cid:18)(cid:16)(cid:20)(cid:14)(cid:12)(cid:18)(cid:1) (cid:22)(cid:21)(cid:7)(cid:5) (cid:6)(cid:14)(cid:19)(cid:13)(cid:23) SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 30 pF PARAMETER MEASUREMENT INFORMATION From Output Test High-Level 3 V Under Test Point Pulse 1.3 V 1.3 V 0 V CL = 50 pF (see Note A) tw 3 V Low-Level LOAD CIRCUIT Pulse 1.3 V 1.3 V 0 V 3 V VOLTAGE WAVEFORMS Input 1.3 V 1.3 V PULSE DURATIONS 0 V tPLH tPHL In-Phase VOH Reference 3 V 90% 90% 1.3 V Output 1.3 V 1.3 V Input 10% 10% VOL 0 V tr tf tsu th tPHL tPLH Out-of- VOH Data 2.7 V 2.7 V 3 V Phase 90% 1.3 V 1.3 V 90% Input 1.3 V 1.3 V 0.3 V 0.3 V Output 10% 10% 0 V VOL tf tr tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HCT273DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 & no Sb/Br) SN74HCT273DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74HCT273N (RoHS) SN74HCT273NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT273 & no Sb/Br) SN74HCT273PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 & no Sb/Br) SN74HCT273PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 & no Sb/Br) SN74HCT273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 & no Sb/Br) SN74HCT273PWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT273 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HCT273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HCT273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74HCT273NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74HCT273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74HCT273PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HCT273DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74HCT273DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HCT273NSR SO NS 20 2000 367.0 367.0 45.0 SN74HCT273PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HCT273PWT TSSOP PW 20 250 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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