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  • 型号: SN74HCT139DR
  • 制造商: Texas Instruments
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ICGOO电子元器件商城为您提供SN74HCT139DR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74HCT139DR价格参考¥0.74-¥2.12。Texas InstrumentsSN74HCT139DR封装/规格:逻辑 - 信号开关,多路复用器,解码器, Decoder/Demultiplexer 1 x 2:4 16-SOIC。您可以下载SN74HCT139DR参考资料、Datasheet数据手册功能说明书,资料中有SN74HCT139DR 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC DECODER/DEMUX DL 2-4L 16-SOIC编码器、解码器、复用器和解复用器 Dual 2 to 4-Line Decdr/Demltplxer

产品分类

逻辑 - 信号开关,多路复用器,解码器

品牌

Texas Instruments

产品手册

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产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

逻辑集成电路,编码器、解码器、复用器和解复用器,Texas Instruments SN74HCT139DR74HCT

数据手册

点击此处下载产品Datasheet

产品型号

SN74HCT139DR

产品

Decoders / Demultiplexers

产品种类

编码器、解码器、复用器和解复用器

供应商器件封装

16-SOIC N

其它名称

296-31833-1

包装

剪切带 (CT)

单位重量

141.700 mg

商标

Texas Instruments

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

16-SOIC(0.154",3.90mm 宽)

封装/箱体

SOIC-16

工作温度

-40°C ~ 85°C

工作温度范围

- 40 C to + 85 C

工作电压

4.5 V to 5.5 V

工厂包装数量

2500

最大工作温度

+ 85 C

最小工作温度

- 40 C

标准包装

1

独立电路

2

电压-电源

4.5 V ~ 5.5 V

电压源

单电源

电流-输出高,低

4mA,4mA

电源电压-最大

5.5 V

电源电压-最小

4.5 V

电路

1 x 2:4

类型

解码器/多路分解器

系列

SN74HCT139

输入/输出线数量

2 / 4

输入线路数量

2

输出线路数量

4

逻辑系列

HCT

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PDF Datasheet 数据手册内容提取

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:13)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:7)(cid:21) (cid:4)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:13)(cid:20)(cid:6)(cid:21)(cid:13)(cid:20)(cid:22)(cid:1)(cid:23)(cid:13)(cid:20)(cid:24)(cid:14)(cid:16)(cid:7)(cid:19)(cid:25)(cid:16)(cid:20)(cid:26)(cid:20)(cid:22)(cid:1) SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003 (cid:1) Operating Voltage Range of 4.5 V to 5.5 V SN54HCT139...J OR W PACKAGE (cid:1) SN74HCT139...D, DB, N, OR PW PACKAGE Outputs Can Drive Up To 10 LSTTL Loads (TOP VIEW) (cid:1) Low Power Consumption, 80-µA Max I CC (cid:1) Typical tpd = 10 ns 1G 1 16 VCC (cid:1) ±4-mA Output Drive at 5 V 1A 2 15 2G (cid:1) Low Input Current of 1 µA Max 1B 3 14 2A 1Y0 4 13 2B (cid:1) Inputs Are TTL-Voltage Compatible 1Y1 5 12 2Y0 (cid:1) Designed Specifically for High-Speed 1Y2 6 11 2Y1 Memory Decoders and Data-Transmission 1Y3 7 10 2Y2 Systems GND 8 9 2Y3 (cid:1) Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception SN54HCT139...FK PACKAGE (TOP VIEW) description/ordering information C A G C CG 1 1 N V 2 The ’HCT139 devices are designed for high-performance memory-decoding or 1B 43 2 1 20 1918 2A data-routing applications requiring very short 1Y0 5 17 2B propagation delay times. In high-performance NC 6 16 NC memory systems, these decoders can minimize 1Y1 7 15 2Y0 the effects of system decoding. When employed 1Y2 8 14 2Y1 with high-speed memories utilizing a fast enable 9 10 1112 13 circuit, the delay time of these decoders and the 3D C 32 enable time of the memory usually are less than YN N YY 1G 22 the typical access time of the memory. This means that the effective system delay introduced by the NC − No internal connection decoders is negligible. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HCT139N SN74HCT139N Tube of 40 SN74HCT139D SSOOIICC −− DD Reel of 2500 SN74HCT139DR HHCCTT113399 −−4400°CC ttoo 8855°CC Reel of 250 SN74HCT139DT SSOP − DB Reel of 2000 SN74HCT139DBR HT139 Reel of 2000 SN74HCT139PWR TTSSSSOOPP −− PPWW HHTT113399 Reel of 250 SN74HCT139PWT CDIP − J Tube of 25 SNJ54HCT139J SNJ54HCT139J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HCT139W SNJ54HCT139W LCCC − FK Tube of 55 SNJ54HCT139FK SNJ54HCT139FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:14)(cid:2)(cid:16)(cid:20)(cid:1)(cid:1) (cid:21)(cid:7)(cid:5)(cid:20)(cid:22)(cid:27)(cid:19)(cid:1)(cid:20) (cid:2)(cid:21)(cid:7)(cid:20)(cid:13) (cid:28)(cid:29)(cid:30)(cid:31) !"#$%&’(cid:28) #"’(cid:28)((cid:30)’(cid:31) (cid:25)(cid:22)(cid:21)(cid:13)(cid:14)(cid:6)(cid:7)(cid:19)(cid:21)(cid:2) Copyright  2003, Texas Instruments Incorporated (cid:13)(cid:15)(cid:7)(cid:15) (cid:30)’)"*%((cid:28)(cid:30)"’ #$**&’(cid:28) ((cid:31) ") +$,-(cid:30)#((cid:28)(cid:30)"’ !((cid:28)&. (cid:25)*"!$#(cid:28)(cid:31) #"’)"*% (cid:28)" (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) +&* (cid:28)(cid:29)& (cid:28)&*%(cid:31) ") (cid:7)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) (cid:31)(cid:28)(’!(*! 0(**(’(cid:28)1. (cid:25)*"!$#(cid:28)(cid:30)"’ +*"#&(cid:31)(cid:31)(cid:30)’2 !"&(cid:31) ’"(cid:28) ’&#&(cid:31)(cid:31)(*(cid:30)-1 (cid:30)’#-$!& (cid:28)&(cid:31)(cid:28)(cid:30)’2 ") (-- +(*(%&(cid:28)&*(cid:31). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:13)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:7)(cid:21) (cid:4)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:13)(cid:20)(cid:6)(cid:21)(cid:13)(cid:20)(cid:22)(cid:1)(cid:23)(cid:13)(cid:20)(cid:24)(cid:14)(cid:16)(cid:7)(cid:19)(cid:25)(cid:16)(cid:20)(cid:26)(cid:20)(cid:22)(cid:1) SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) The ’HCT139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. FUNCTION TABLE INPUTS OOUUTTPPUUTTSS SELECT GG B A Y0 Y1 Y2 Y3 H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L logic diagram (positive logic) 4 1Y0 1 1G 5 1Y1 6 1Y2 2 1A 7 3 1Y3 1B 12 2Y0 15 2G 11 2Y1 10 2Y2 14 2A 9 13 2Y3 2B Pin numbers shown are for the D, DB, J, N, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:13)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:7)(cid:21) (cid:4)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:13)(cid:20)(cid:6)(cid:21)(cid:13)(cid:20)(cid:22)(cid:1)(cid:23)(cid:13)(cid:20)(cid:24)(cid:14)(cid:16)(cid:7)(cid:19)(cid:25)(cid:16)(cid:20)(cid:26)(cid:20)(cid:22)(cid:1) SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT139 SN74HCT139 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V tt Input transition (rise and fall) time 500 500 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT139 SN74HCT139 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −20 µA 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44..55 VV VV IOH = −4 mA 3.98 4.3 3.7 3.84 IOL = 20 µA 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44..55 VV VV IOL = 4 mA 0.17 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V, ∆ICC‡ Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA 4.5 V Ci to 5.5 V 3 10 10 10 pF ‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. (cid:25)(cid:22)(cid:21)(cid:13)(cid:14)(cid:6)(cid:7) (cid:25)(cid:22)(cid:20)3(cid:19)(cid:20)(cid:27) (cid:30)’)"*%((cid:28)(cid:30)"’ #"’#&*’(cid:31) +*"!$#(cid:28)(cid:31) (cid:30)’ (cid:28)(cid:29)& )"*%((cid:28)(cid:30)4& "* !&(cid:31)(cid:30)2’ +(cid:29)((cid:31)& ") !&4&-"+%&’(cid:28). (cid:6)(cid:29)(*(#(cid:28)&*(cid:30)(cid:31)(cid:28)(cid:30)# !((cid:28)( (’! "(cid:28)(cid:29)&* (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) (*& !&(cid:31)(cid:30)2’ 2"(-(cid:31). (cid:7)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) *&(cid:31)&*4&(cid:31) (cid:28)(cid:29)& *(cid:30)2(cid:29)(cid:28) (cid:28)" #(cid:29)(’2& "* !(cid:30)(cid:31)#"’(cid:28)(cid:30)’$& (cid:28)(cid:29)&(cid:31)& +*"!$#(cid:28)(cid:31) 0(cid:30)(cid:28)(cid:29)"$(cid:28) ’"(cid:28)(cid:30)#&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:13)(cid:14)(cid:15)(cid:16) (cid:17)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:7)(cid:21) (cid:4)(cid:18)(cid:16)(cid:19)(cid:2)(cid:20) (cid:13)(cid:20)(cid:6)(cid:21)(cid:13)(cid:20)(cid:22)(cid:1)(cid:23)(cid:13)(cid:20)(cid:24)(cid:14)(cid:16)(cid:7)(cid:19)(cid:25)(cid:16)(cid:20)(cid:26)(cid:20)(cid:22)(cid:1) SCLS066D − MARCH 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HCT139 SN74HCT139 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 4.5 V 14 34 51 43 AA oorr BB YY 5.5 V 12 30 50 40 ttppdd nnss 4.5 V 11 34 51 43 GG YY 5.5 V 10 30 50 40 4.5 V 8 15 22 19 tttt YY nnss 5.5 V 6 14 21 17 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per decoder No load 25 pF PARAMETER MEASUREMENT INFORMATION 3 V From Output Test Under Test Point Input 1.3 V 1.3 V 0 V CL = 50 pF (see Note A) tPLH tPHL In-Phase VOH 90% 90% Output 1.3 V 1.3 V LOAD CIRCUIT 10% 10% VOL tr tf tPHL tPLH 3 V Input 1.3 V 2.7 V 2.7 V 1.3 V Out-of-Phase 90% 1.3 V 1.3 V 90% VOH 0.3 V 0.3 V 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms (cid:25)(cid:22)(cid:21)(cid:13)(cid:14)(cid:6)(cid:7) (cid:25)(cid:22)(cid:20)3(cid:19)(cid:20)(cid:27) (cid:30)’)"*%((cid:28)(cid:30)"’ #"’#&*’(cid:31) +*"!$#(cid:28)(cid:31) (cid:30)’ (cid:28)(cid:29)& )"*%((cid:28)(cid:30)4& "* !&(cid:31)(cid:30)2’ +(cid:29)((cid:31)& ") !&4&-"+%&’(cid:28). (cid:6)(cid:29)(*(#(cid:28)&*(cid:30)(cid:31)(cid:28)(cid:30)# !((cid:28)( (’! "(cid:28)(cid:29)&* (cid:31)+&#(cid:30))(cid:30)#((cid:28)(cid:30)"’(cid:31) (*& !&(cid:31)(cid:30)2’ 2"(-(cid:31). (cid:7)&/((cid:31) (cid:19)’(cid:31)(cid:28)*$%&’(cid:28)(cid:31) *&(cid:31)&*4&(cid:31) (cid:28)(cid:29)& *(cid:30)2(cid:29)(cid:28) (cid:28)" #(cid:29)(’2& "* !(cid:30)(cid:31)#"’(cid:28)(cid:30)’$& (cid:28)(cid:29)&(cid:31)& +*"!$#(cid:28)(cid:31) 0(cid:30)(cid:28)(cid:29)"$(cid:28) ’"(cid:28)(cid:30)#&. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HCT139D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT139 & no Sb/Br) SN74HCT139DBR ACTIVE SSOP DB 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT139 & no Sb/Br) SN74HCT139DE4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT139 & no Sb/Br) SN74HCT139DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT139 & no Sb/Br) SN74HCT139N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HCT139N & no Sb/Br) SN74HCT139PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT139 & no Sb/Br) SN74HCT139PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT139 & no Sb/Br) SN74HCT139PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT139 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HCT139DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HCT139PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HCT139PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HCT139DR SOIC D 16 2500 333.2 345.9 28.6 SN74HCT139PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HCT139PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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