(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:9)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:7)(cid:17) (cid:10)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:18)(cid:16)(cid:6)(cid:17)(cid:18)(cid:16)(cid:19)(cid:1)(cid:20)(cid:18)(cid:16)(cid:21)(cid:22)(cid:14)(cid:7)(cid:15)(cid:23)(cid:14)(cid:16)(cid:24)(cid:16)(cid:19)(cid:1) SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003 (cid:1) Operating Voltage Range of 4.5 V to 5.5 V (cid:1) Low Input Current of 1 µA Max (cid:1) (cid:1) Outputs Can Drive Up To 10 LSTTL Loads Inputs Are TTL-Voltage Compatible (cid:1) Low Power Consumption, 80-µA Max I (cid:1) Designed Specifically for High-Speed CC (cid:1) Memory Decoders and Data Transmission Typical tpd = 17 ns (cid:1) ±4-mA Output Drive at 5 V Systems (cid:1) Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception SN54HCT138...J OR W PACKAGE SN54HCT138...FK PACKAGE SN74HCT138...D, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) C C C0 B A N V Y A 1 16 VCC B 2 15 Y0 C 43 2 1 20 1918 Y1 C 3 14 Y1 G2A 5 17 Y2 G2A 4 13 Y2 NC 6 16 NC G2B 5 12 Y3 G2B 7 15 Y3 G1 6 11 Y4 G1 8 14 Y4 Y7 7 10 Y5 9 10 1112 13 GND 8 9 Y6 7D C6 5 YN NY Y G NC − No internal connection description/ordering information The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HCT138N SN74HCT138N Tube of 40 SN74HCT138D SSOOIICC −− DD Reel of 2500 SN74HCT138DR HHCCTT113388 Reel of 250 SN74HCT138DT −−4400°°CC ttoo 8855°°CC SOP − NS Reel of 2000 SN74HCT138NSR HCT138 Tube of 90 SN74HCT138PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HCT138PWR HHTT113388 Reel of 250 SN74HCT138PWT CDIP − J Tube of 25 SNJ54HCT138J SNJ54HCT138J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HCT138W SNJ54HCT138W LCCC − FK Tube of 55 SNJ54HCT138FK SNJ54HCT138FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:23)(cid:19)(cid:17)(cid:18)(cid:22)(cid:6)(cid:7)(cid:15)(cid:17)(cid:2) (cid:18)(cid:25)(cid:7)(cid:25) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2003, Texas Instruments Incorporated (cid:23)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:7)&-!# (cid:15)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# (cid:17)(cid:27) ’(cid:30)(cid:29)*%$"# $(cid:29)(cid:31)’)(cid:26)!(cid:27)" "(cid:29) (cid:21)(cid:15)(cid:14)(cid:13)(cid:23)(cid:19)1(cid:13)(cid:9)(cid:10)(cid:3)(cid:9)(cid:3)(cid:11) !)) ’!(cid:30)!(cid:31)&"&(cid:30)# !(cid:30)& "&#"&* #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:23)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& %(cid:27))&## (cid:29)",&(cid:30).(cid:26)#& (cid:27)(cid:29)"&*+ (cid:17)(cid:27) !)) (cid:29)",&(cid:30) ’(cid:30)(cid:29)*%$"#(cid:11) ’(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:9)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:7)(cid:17) (cid:10)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:18)(cid:16)(cid:6)(cid:17)(cid:18)(cid:16)(cid:19)(cid:1)(cid:20)(cid:18)(cid:16)(cid:21)(cid:22)(cid:14)(cid:7)(cid:15)(cid:23)(cid:14)(cid:16)(cid:24)(cid:16)(cid:19)(cid:1) SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003 description/ordering information (continued) The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. FUNCTION TABLE INPUTS OOUUTTPPUUTTSS ENABLE SELECT G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:9)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:7)(cid:17) (cid:10)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:18)(cid:16)(cid:6)(cid:17)(cid:18)(cid:16)(cid:19)(cid:1)(cid:20)(cid:18)(cid:16)(cid:21)(cid:22)(cid:14)(cid:7)(cid:15)(cid:23)(cid:14)(cid:16)(cid:24)(cid:16)(cid:19)(cid:1) SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 15 Y0 1 A 14 Y1 2 B 13 Y2 3 12 C Y3 11 Y4 10 Y5 6 G1 9 Y6 4 G2A 7 Y7 5 G2B Pin numbers shown are for the D, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:9)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:7)(cid:17) (cid:10)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:18)(cid:16)(cid:6)(cid:17)(cid:18)(cid:16)(cid:19)(cid:1)(cid:20)(cid:18)(cid:16)(cid:21)(cid:22)(cid:14)(cid:7)(cid:15)(cid:23)(cid:14)(cid:16)(cid:24)(cid:16)(cid:19)(cid:1) SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HCT138 SN74HCT138 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V ∆t/∆v Input transition rise/fall time 500 500 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT138 SN74HCT138 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −20 µA 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44..55 VV VV IOH = −4 mA 3.98 4.3 3.7 3.84 IOL = 20 µA 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44..55 VV VV IOL = 4 mA 0.17 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V, ∆ICC† Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA 4.5 V Ci to 5.5 V 3 10 10 10 pF †This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HCT138 SN74HCT138 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 4.5 V 23 36 54 45 AA,, BB,, oorr CC AAnnyy YY 5.5 V 17 32 49 34 ttppdd nnss 4.5 V 22 33 50 42 EEnnaabbllee AAnnyy YY 5.5 V 18 30 45 38 4.5 V 12 15 22 19 tttt YY nnss 5.5 V 11 14 20 17 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 85 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:12)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:9)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:7)(cid:17) (cid:10)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16) (cid:18)(cid:16)(cid:6)(cid:17)(cid:18)(cid:16)(cid:19)(cid:1)(cid:20)(cid:18)(cid:16)(cid:21)(cid:22)(cid:14)(cid:7)(cid:15)(cid:23)(cid:14)(cid:16)(cid:24)(cid:16)(cid:19)(cid:1) SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION 3 V From Output Test Under Test Point Input 1.3 V 1.3 V 0 V CL = 50 pF (see Note A) tPLH tPHL In-Phase VOH 90% 90% Output 1.3 V 1.3 V LOAD CIRCUIT 10% 10% VOL tr tf tPHL tPLH 3 V Input 1.3 V 2.7 V 2.7 V 1.3 V Out-of-Phase 90% 1.3 V 1.3 V 90% VOH 0.3 V 0.3 V 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 85504012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85504012A SNJ54HCT 138FK 8550401EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8550401EA SNJ54HCT138J 8550401FA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8550401FA SNJ54HCT138W JM38510/65852BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65852BEA M38510/65852BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65852BEA SN54HCT138J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HCT138J SN74HCT138D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138DT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HCT138N & no Sb/Br) SN74HCT138NE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HCT138N & no Sb/Br) SN74HCT138NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HCT138 & no Sb/Br) SN74HCT138PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT138 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HCT138PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HT138 & no Sb/Br) SN74HCT138PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HT138 & no Sb/Br) SNJ54HCT138FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85504012A SNJ54HCT 138FK SNJ54HCT138J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8550401EA SNJ54HCT138J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HCT138, SN74HCT138 : •Catalog: SN74HCT138 •Military: SN54HCT138 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HCT138DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HCT138DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74HCT138DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HCT138NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HCT138PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HCT138PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HCT138PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HCT138DR SOIC D 16 2500 333.2 345.9 28.6 SN74HCT138DR SOIC D 16 2500 364.0 364.0 27.0 SN74HCT138DRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74HCT138NSR SO NS 16 2000 367.0 367.0 38.0 SN74HCT138PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HCT138PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HCT138PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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