Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features 3 Description • WideOperatingVoltageRange:2Vto6V The SNx4HC74 devices contain two independent D- 1 type positive-edge-triggered flip-flops. A low level at • OutputsCanDriveUpTo10LSTTLLoads the preset (PRE) or clear (CLR) inputs sets or resets • LowPowerConsumption,40-µAMaximumICC the outputs, regardless of the levels of the other • Typicalt =15ns inputs. When PRE and CLR are inactive (high), data pd at the data (D) input meeting the setup time • ±4-mAOutputDriveat5V requirements are transferred to the outputs on the • VeryLowInputCurrentof1µA positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly 2 Applications related to the rise time of CLK. Following the hold- time interval, data at the D input can be changed • UltrasoundSystem withoutaffectingthelevelsattheoutputs. • Fans • LabInstrumentation DeviceInformation(1) • VacuumCleaners PARTNUMBER PACKAGE BODYSIZE(NOM) • VideoCommunicationsSystem SN74HC74N PDIP(14) 19.30mmx6.40mm • IPPhone:Wired SN74HC74NS SO(14) 10.20mmx5.30mm SN74HC74D SOIC(14) 8.70mmx3.90mm SN74HC74DB SSOP(14) 6.50mmx5.30mm SN74HC74PW TSSOP(14) 5.00mmx4.40mm SNJ54HC74J CDIP(14) 21.30mmx7.60mm SNJ54HC74W CFP(14) 9.20mmx6.29mm SNJ54HC74FK LCCC(20) 8.90mmx8.90mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. LogicDiagram(PositiveLogic) PRE C CLK C Q C TG C C C C D TG TG TG Q C C C CLR 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................10 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................10 3 Description............................................................. 1 9 ApplicationandImplementation........................ 11 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation ..........................................11 9.2 TypicalApplication .................................................11 5 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 12 6 Specifications......................................................... 4 11 Layout................................................................... 13 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings ............................................................4 11.1 LayoutGuidelines.................................................13 6.3 RecommendedOperatingConditions.......................4 11.2 LayoutExample....................................................13 6.4 ThermalInformation..................................................5 12 DeviceandDocumentationSupport................. 14 6.5 ElectricalCharacteristics...........................................5 12.1 DocumentationSupport........................................14 6.6 TimingRequirements................................................6 12.2 RelatedLinks........................................................14 6.7 SwitchingCharacteristics..........................................7 12.3 CommunityResources..........................................14 6.8 TypicalCharacteristics..............................................8 12.4 Trademarks...........................................................14 7 ParameterMeasurementInformation..................9 12.5 ElectrostaticDischargeCaution............................14 12.6 Glossary................................................................14 8 DetailedDescription............................................ 10 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................10 Information........................................................... 14 8.2 FunctionalBlockDiagram.......................................10 4 Revision History ChangesfromRevisionD(July2003)toRevisionE Page • AddedApplications,DeviceInformationtable,PinFunctionstable,ESDRatingstable,ThermalInformationtable, TypicalCharacteristics,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 5 Pin Configuration and Functions N,NS,D,DB,PW,J,orWPackage FKPackage 14-PinPDIP,SO,SOIC,SSOP,TSSOP,CDIP,orCFP 20-PinLCCC TopView TopView R R 1CLR 1 14 VCC 1D 1CLNC VCC2CL 1D 2 13 2CLR 3 2 1 2019 1CLK 3 12 2D 1CLK 4 18 2D 1PRE 4 11 2CLK NC 5 17 NC 1PRE 6 16 2CLK 1Q 5 10 2PRE NC 7 15 NC 1Q 6 9 2Q 1Q 8 14 2PRE 9 10 1112 13 GND 7 8 2Q QDCQQ 1NN22 G NC–Nointernalconnection PinFunctions PIN SOIC,SSOP,CDIP, I/O DESCRIPTION NAME LCCC PDIP,SO,TSSOP,CFP NO. 1CLK 4 3 I Clockinput 1CLR 2 1 I Clearinput-Pulllowtoset1Qoutputlow 1D 3 2 I Input 1PRE 6 4 I Presetinput 1Q 8 5 O Output 1Q 9 6 O Invertedoutput 2CLK 16 11 I Clockinput 2CLR 19 13 I Clearinput-Pulllowtoset1Qoutputlow 2D 18 12 I Input 2PRE 14 10 I Presetinput 2Q 13 9 O Output 2Q 12 8 O Invertedoutput GND 10 7 — Ground 1 5 7 NC — — Noconnect(nointernalconnection) 11 15 17 V 20 14 — Supply CC Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT V Supplyvoltagerange –0.5 7 V CC I Inputclampcurrent(2) V <0orV >V ±20 mA IK I I CC I Outputclampcurrent(2) V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±50 mA CC T Junctiontemperaturerange 150 °C j T Storagetemperaturerange –65 150 °C stg (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossiblewiththenecessaryprecautions. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan250-VCDMispossiblewiththenecessaryprecautions. 6.3 Recommended Operating Conditions See (1) SN54HC74 SN74HC74 UNIT MIN NOM MAX MIN NOM MAX V Supplyvoltage 2 5 6 2 5 6 V CC V =2V 1.5 1.5 CC V High-levelinputvoltage V =4.5V 3.15 3.15 V IH CC V =6V 4.2 4.2 CC V =2V 0.5 0.5 CC V Low-levelinputvoltage V =4.5V 1.35 1.35 V IL CC V =6V 1.8 1.8 CC V Inputvoltage 0 V 0 V V I CC CC V Outputvoltage 0 V 0 V V O CC CC V =2V 1000 1000 CC ∆t/∆v Inputtransitionriseandfalltime V =4.5V 500 500 ns CC V =6V 400 400 CC T Operatingfree-airtemperature –55 125 –40 85 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. 4 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 6.4 Thermal Information SN74HC74 SN54HC74 THERMALMETRIC(1) D DB N NS PW J W FK UNIT (SOIC) (SSOP) (PDIP) (SO) (TSSOP) (CDIP) (CFP) (LCCC) 14PINS 14PINS 20PINS R Junction-to-ambientthermalresistance 86 96 80 76 113 — — — θJA °C/W R Junction-to-case(top)thermalresistance — — — — — 15.05 14.65 5.61 θJC(top) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange,T =25°C(unlessotherwisenoted) A PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2V 1.9 1.998 I =–20µA 4.5V 4.4 4.499 OH 6V 5.9 5.999 T =25°C 3.98 4.3 A V V =V orV I =–4mA SN54HC74 4.5V 3.7 V OH I IH IL OH SN74HC74 3.84 T =25°C 5.48 5.8 A I =–5.2mA SN54HC74 6V 5.2 OH SN74HC74 5.34 2V 0.002 0.1 I =20µA 4.5V 0.001 0.1 OL 6V 0.001 0.1 T =25°C 0.17 0.26 A V V =V orV I =4mA SN54HC74 4.5V 0.4 V OL I IH IL OL SN74HC74 0.33 T =25°C 0.15 0.26 A I =5.2mA SN54HC74 6V 0.4 OL SN74HC74 0.33 V =V or0 T =25°C ±0.1 ±100 I CC A II SN54HC74, 6V nA ±1000 SN74HC74 V =V or0, I =0 T =25°C 4 I CC O A I SN54HC74 6V 80 µA CC SN74HC74 40 C 2Vto6V 3 10 pF i C Noload 2Vto6V 35 pF pd Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com 6.6 Timing Requirements overrecommendedoperatingfree-airtemperaturerange,T =25°C(unlessotherwisenoted) A V T MIN MAX UNIT CC A T =25°C 6 A 2V SN54HC74 4.2 SN74HC74 5 T =25°C 31 A f Clockfrequency 4.5V SN54HC74 21 MHz clock SN74HC74 25 T =25°C 0 36 A 6V SN54HC74 0 25 SN74HC74 0 29 T =25°C 100 A 2V SN54HC74 150 SN74HC74 125 T =25°C 20 A PREorCLRlow 4.5V SN54HC74 30 SN74HC74 25 T =25°C 14 A 6V SN54HC74 25 SN74HC74 21 t Pulseduration ns w T =25°C 80 A 2V SN54HC74 120 SN74HC74 100 T =25°C 16 A CLKhighorlow 4.5V SN54HC74 24 SN74HC74 20 T =25°C 14 A 6V SN54HC74 20 SN74HC74 17 T =25°C 100 A 2V SN54HC74 150 SN74HC74 125 T =25°C 20 A Data 4.5V SN54HC74 30 SN74HC74 25 T =25°C 17 A 6V SN54HC74 25 Setuptimebefore SN74HC74 21 t ns su CLK↑ T =25°C 25 A 2V SN54HC74 40 SN74HC74 30 T =25°C 5 A PREorCLRinactive 4.5V SN54HC74 8 SN74HC74 6 T =25°C 4 A 6V SN54HC74 7 SN74HC74 5 6 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 Timing Requirements (continued) overrecommendedoperatingfree-airtemperaturerange,T =25°C(unlessotherwisenoted) A V T MIN MAX UNIT CC A 2V 0 t Holdtime,dataafterCLK↑ 4.5V 0 ns h 6V 0 6.7 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =50pF(unlessotherwisenoted)(seeFigure2) L FROM TO PARAMETER V T MIN TYP MAX UNIT (INPUT) (OUTPUT) CC A T =25°C 6 10 A 2V SN54HC74 4.2 SN74HC74 6 T =25°C 31 50 A f 4.5V SN54HC74 21 MHz max SN74HC74 25 T =25°C 36 60 A 6V SN54HC74 25 SN74HC74 29 T =25°C 70 230 A 2V SN54HC74 345 SN74HC74 290 T =25°C 20 46 A PREorCLR QorQ 4.5V SN54HC74 69 SN74HC74 58 T =25°C 15 39 A 6V SN54HC74 59 SN74HC74 49 t ns pd T =25°C 70 175 A 2V SN54HC74 250 SN74HC74 220 T =25°C 20 35 A CLK QorQ 4.5V SN54HC74 50 SN74HC74 44 T =25°C 15 30 A 6V SN54HC74 42 SN74HC74 37 T =25°C 28 75 A 2V SN54HC74 110 SN74HC74 95 T =25°C 8 15 A t QorQ 4.5V SN54HC74 22 ns t SN74HC74 19 T =25°C 6 13 A 6V SN54HC74 19 SN74HC74 16 Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com 6.8 Typical Characteristics 75 60 45 tpd(ns) 30 15 0 0 1.5 3 4.5 6 7.5 VCC (V) Figure1.TypicalPropagationDelay-CLKtoQ 8 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 7 Parameter Measurement Information FromOutput Test High-Level VCC 50% 50% UnderTest Point Pulse 0V CL=50pF (seeNoteA) tw Low-Level VCC Pulse 50% 50% LOADCIRCUIT 0V VOLTAGEWAVEFORMS PULSEDURATIONS VCC VCC Reference 50% Input 50% 50% Input 0V 0V tsu th tPLH tPHL Data 90% 90% VCC In-Phase 90% 90% VOH Input 50% 50% Output 50% 50% 10% 10% 10% 10% 0V VOL tr tf tr tf tPHL tPLH VOLTAGEWAVEFORMS VOH SETUPANDHOLDANDINPUTRISEANDFALLTIMES Out-of-Phase 90% 50% 50% 90% Output 10% 10% VOL tf tr VOLTAGEWAVEFORMS PROPAGATIONDELAYANDOUTPUTTRANSITIONTIMES A. C includesprobeandtest-fixturecapacitance. L B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having thefollowingcharacteristics:PRR≤1MHz,Z =50Ω,t =6ns,t =6ns. O r f C. Forclockinputs,f ismeasuredwhentheinputdutycycleis50%. max D. Theoutputsaremeasuredoneatatimewithoneinputtransitionpermeasurement. E. t andt arethesameast . PLH PHL pd Figure2. LoadCircuitandVoltageWaveforms Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com 8 Detailed Description 8.1 Overview Figure 3 describes the SNx4HC74 devices. As the SNx4HC74 is a dual D-Type positive-edge-triggered flip-flop withclearandpreset,thediagrambelowdescribesoneofthetwodeviceflip-flops. 8.2 Functional Block Diagram PRE C CLK C Q C TG C C C C D TG TG TG Q C C C CLR Figure3. LogicDiagram(PositiveLogic) 8.3 Feature Description The SNx4HC74 inputs accept voltage levels up to 5.5 V. Refer to the Recommended Operating Conditions for appropriateinputhighandlowlogiclevels. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSNx4HC74. Table1.FunctionTable INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q Q 0 0 (1) Thisconfigurationisnonstable;thatis,itdoesnotpersistwhenPREorCLRreturnstoitsinactive (high)level. 10 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, dataattheDinputcanbechangedwithoutaffectingthelevelsattheoutputs. The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected directlytoV tobeinactive. CC 9.2 Typical Application 5 V 5 V 5 V SN74LVC1G17 SN74HC74 Figure4. DevicePowerButtonCircuit 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. Outputs may be combined to produce higher drive, but the high drive will also create faster edges into light loads. Because of this, routing and load conditions should be consideredtopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions: – Forrisetimeandfalltimespecifications,see(Δt/ΔV)inRecommendedOperatingConditions table. – Forspecifiedhighandlowlevels,see(V andV )inRecommendedOperatingConditions table. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV . CC 2. RecommendedOutputConditions: – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – Series resistors on the output may be used if the user desires to slow the output edge signal or limit the outputcurrent. Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve 75 60 45 tpd(ns) 30 15 0 0 1.5 3 4.5 6 7.5 VCC (V) Figure5.TypicalPropagationDelay- CLRtoQ 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each V terminal should have a good bypass capacitor to prevent CC powerdisturbance.Fordeviceswithasinglesupply,a0.1-μFcapacitorisrecommendedandiftherearemultiple V terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable to CC parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible forbestresults. 12 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 www.ti.com SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or V , whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a CC transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted. ThispinkeepstheinputsectionoftheI/Osfrombeingdisabledandfloated. 11.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure6. LayoutDiagram Copyright©1982–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN54HC74 SN74HC74

SN54HC74,SN74HC74 SCLS094E–DECEMBER1982–REVISEDDECEMBER2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs,SCBA004 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54HC74 Clickhere Clickhere Clickhere Clickhere Clickhere SN74HC74 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 14 SubmitDocumentationFeedback Copyright©1982–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC74 SN74HC74

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8405601VCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8405601VC A SNV54HC74J 5962-8405601VDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8405601VD A SNV54HC74W 84056012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84056012A SNJ54HC 74FK 8405601CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8405601CA SNJ54HC74J 8405601DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8405601DA SNJ54HC74W JM38510/65302B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65302B2A JM38510/65302BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65302BCA JM38510/65302BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65302BDA M38510/65302B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65302B2A M38510/65302BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65302BCA M38510/65302BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65302BDA SN54HC74J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HC74J SN74HC74D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HC74DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N & no Sb/Br) SN74HC74NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N & no Sb/Br) SN74HC74NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SN74HC74PWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 & no Sb/Br) SNJ54HC74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84056012A SNJ54HC 74FK SNJ54HC74J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8405601CA SNJ54HC74J SNJ54HC74W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8405601DA SNJ54HC74W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 : •Catalog: SN74HC74, SN54HC74 •Automotive: SN74HC74-Q1, SN74HC74-Q1 •Enhanced Product: SN74HC74-EP, SN74HC74-EP •Military: SN54HC74 •Space: SN54HC74-SP Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC74DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1 SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC74PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC74DR SOIC D 14 2500 364.0 364.0 27.0 SN74HC74DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC74DRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74HC74DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC74DT SOIC D 14 250 210.0 185.0 35.0 SN74HC74PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC74PWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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