(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:16)(cid:19)(cid:1)(cid:20)(cid:21)(cid:20)(cid:22)(cid:18)(cid:23)(cid:13)(cid:2)(cid:14) (cid:24)(cid:13)(cid:21)(cid:18)(cid:1) (cid:25)(cid:20)(cid:21)(cid:5) (cid:1)(cid:6)(cid:5)(cid:26)(cid:20)(cid:21)(cid:21)(cid:23)(cid:21)(cid:15)(cid:20)(cid:24)(cid:24)(cid:18)(cid:15) (cid:20)(cid:2)(cid:16)(cid:12)(cid:21)(cid:1) SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004 (cid:1) Wide Operating Voltage Range of 2 V to 6 V SN54HC7001...J OR W PACKAGE (cid:1) SN74HC7001...D, N, OR NS PACKAGE Operation From Very Slow Input (TOP VIEW) Transitions (cid:1) Same Pinouts as ’HC08 1A 1 14 VCC (cid:1) Outputs Can Drive Up To 10 LSTTL Loads 1B 2 13 4B (cid:1) Low Power Consumption, 20-µA Max I 1Y 3 12 4A CC (cid:1) 2A 4 11 4Y Typical tpd = 14 ns (cid:1) ±4-mA Output Drive at 5 V 2B 5 10 3B 2Y 6 9 3A (cid:1) Low Input Current of 1 µA Max GND 7 8 3Y (cid:1) Allow Design of Either RC or Crystal Oscillator Circuits (cid:1) SN54HC7001...FK PACKAGE Temperature-Compensated Threshold (TOP VIEW) Levels C (cid:1) High Noise Immunity 1B 1A NC VC4B description/ordering information 3 2 1 20 19 1Y 4 18 4A NC 5 17 NC Each circuit functions as a quadruple AND gate. 2A 6 16 4Y They perform the Boolean function NC 7 15 NC Y(cid:1)A•BorY(cid:1)A(cid:2)B in positive logic. 2B 8 14 3B Because of the Schmitt action, the inputs have 9 10 1112 13 different input threshold levels for positive- and YD CY A negative-going signals. 2N N3 3 G These circuits are temperature compensated and can be triggered from the slowest of input ramps NC − No internal connection and still give clean jitter-free output signals. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC7001N SN74HC7001N Tube of 50 SN74HC7001D −−4400°CC ttoo 8855°CC SSOOIICC −− DD Reel of 2500 SN74HC7001DR HHCC77000011 Reel of 250 SN74HC7001DT SOP − NS Reel of 2000 SN74HC7001NSR HC7001 CDIP − J Tube of 25 SNJ54HC7001J SNJ54HC7001J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC7001W SNJ54HC7001W LCCC − FK Tube of 55 SNJ54HC7001FK SNJ54HC7001FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:12)(cid:2)(cid:17)(cid:18)(cid:1)(cid:1) (cid:19)(cid:21)(cid:5)(cid:18)(cid:15)(cid:25)(cid:20)(cid:1)(cid:18) (cid:2)(cid:19)(cid:21)(cid:18)(cid:14) (cid:27)(cid:28)(cid:29)(cid:30) (cid:31)!"#$%&(cid:27) "!&(cid:27)’(cid:29)&(cid:30) (cid:16)(cid:15)(cid:19)(cid:14)(cid:12)(cid:6)(cid:21)(cid:20)(cid:19)(cid:2) Copyright  2004, Texas Instruments Incorporated (cid:14)(cid:13)(cid:21)(cid:13) (cid:29)&(!)$’(cid:27)(cid:29)!& "#))%&(cid:27) ’(cid:30) !( *#+,(cid:29)"’(cid:27)(cid:29)!& (cid:31)’(cid:27)%- (cid:16))!(cid:31)#"(cid:27)(cid:30) "!&(!)$ (cid:27)! (cid:30)*%"(cid:29)((cid:29)"’(cid:27)(cid:29)!&(cid:30) *%) (cid:27)(cid:28)% (cid:27)%)$(cid:30) !( (cid:21)%.’(cid:30) (cid:20)&(cid:30)(cid:27))#$%&(cid:27)(cid:30) (cid:30)(cid:27)’&(cid:31)’)(cid:31) /’))’&(cid:27)0- (cid:16))!(cid:31)#"(cid:27)(cid:29)!& *)!"%(cid:30)(cid:30)(cid:29)&1 (cid:31)!%(cid:30) &!(cid:27) &%"%(cid:30)(cid:30)’)(cid:29),0 (cid:29)&",#(cid:31)% (cid:27)%(cid:30)(cid:27)(cid:29)&1 !( ’,, *’)’$%(cid:27)%)(cid:30)- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:16)(cid:19)(cid:1)(cid:20)(cid:21)(cid:20)(cid:22)(cid:18)(cid:23)(cid:13)(cid:2)(cid:14) (cid:24)(cid:13)(cid:21)(cid:18)(cid:1) (cid:25)(cid:20)(cid:21)(cid:5) (cid:1)(cid:6)(cid:5)(cid:26)(cid:20)(cid:21)(cid:21)(cid:23)(cid:21)(cid:15)(cid:20)(cid:24)(cid:24)(cid:18)(cid:15) (cid:20)(cid:2)(cid:16)(cid:12)(cid:21)(cid:1) SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004 FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H H H L X L X L L logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC7001 SN74HC7001 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (cid:16)(cid:15)(cid:19)(cid:14)(cid:12)(cid:6)(cid:21) (cid:16)(cid:15)(cid:18)(cid:22)(cid:20)(cid:18)(cid:25) (cid:29)&(!)$’(cid:27)(cid:29)!& "!&"%)&(cid:30) *)!(cid:31)#"(cid:27)(cid:30) (cid:29)& (cid:27)(cid:28)% (!)$’(cid:27)(cid:29)2% !) (cid:31)%(cid:30)(cid:29)1& *(cid:28)’(cid:30)% !( (cid:31)%2%,!*$%&(cid:27)- (cid:6)(cid:28)’)’"(cid:27)%)(cid:29)(cid:30)(cid:27)(cid:29)" (cid:31)’(cid:27)’ ’&(cid:31) !(cid:27)(cid:28)%) (cid:30)*%"(cid:29)((cid:29)"’(cid:27)(cid:29)!&(cid:30) ’)% (cid:31)%(cid:30)(cid:29)1& 1!’,(cid:30)- (cid:21)%.’(cid:30) (cid:20)&(cid:30)(cid:27))#$%&(cid:27)(cid:30) )%(cid:30)%)2%(cid:30) (cid:27)(cid:28)% )(cid:29)1(cid:28)(cid:27) (cid:27)! "(cid:28)’&1% !) (cid:31)(cid:29)(cid:30)"!&(cid:27)(cid:29)&#% (cid:27)(cid:28)%(cid:30)% *)!(cid:31)#"(cid:27)(cid:30) /(cid:29)(cid:27)(cid:28)!#(cid:27) &!(cid:27)(cid:29)"%- 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:16)(cid:19)(cid:1)(cid:20)(cid:21)(cid:20)(cid:22)(cid:18)(cid:23)(cid:13)(cid:2)(cid:14) (cid:24)(cid:13)(cid:21)(cid:18)(cid:1) (cid:25)(cid:20)(cid:21)(cid:5) (cid:1)(cid:6)(cid:5)(cid:26)(cid:20)(cid:21)(cid:21)(cid:23)(cid:21)(cid:15)(cid:20)(cid:24)(cid:24)(cid:18)(cid:15) (cid:20)(cid:2)(cid:16)(cid:12)(cid:21)(cid:1) SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC7001 SN74HC7001 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 0.7 1.2 1.5 0.7 1.5 0.7 1.5 VVTT++ 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 VV 6 V 2.1 3.3 4.2 2.1 4.2 2.1 4.2 2 V 0.3 0.6 1 0.3 1 0.3 1 VVTT−− 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 VV 6 V 1.2 2 3.2 1.2 3.2 1.2 3.2 2 V 0.2 0.6 1.2 0.2 1.2 0.2 1.2 VV VVTT++ −− VVTT−− 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 6 V 0.5 1.3 2.5 0.5 2.5 0.5 2.5 V 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA Ci 2 V to 6 V 3 10 10 10 pF switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC7001 SN74HC7001 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 60 130 195 163 ttppdd AA oorr BB YY 4.5 V 18 26 39 33 nnss 6 V 14 22 33 28 2 V 28 75 110 95 tttt AAnnyy 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate No load 20 pF (cid:16)(cid:15)(cid:19)(cid:14)(cid:12)(cid:6)(cid:21) (cid:16)(cid:15)(cid:18)(cid:22)(cid:20)(cid:18)(cid:25) (cid:29)&(!)$’(cid:27)(cid:29)!& "!&"%)&(cid:30) *)!(cid:31)#"(cid:27)(cid:30) (cid:29)& (cid:27)(cid:28)% (!)$’(cid:27)(cid:29)2% !) (cid:31)%(cid:30)(cid:29)1& *(cid:28)’(cid:30)% !( (cid:31)%2%,!*$%&(cid:27)- (cid:6)(cid:28)’)’"(cid:27)%)(cid:29)(cid:30)(cid:27)(cid:29)" (cid:31)’(cid:27)’ ’&(cid:31) !(cid:27)(cid:28)%) (cid:30)*%"(cid:29)((cid:29)"’(cid:27)(cid:29)!&(cid:30) ’)% (cid:31)%(cid:30)(cid:29)1& 1!’,(cid:30)- (cid:21)%.’(cid:30) (cid:20)&(cid:30)(cid:27))#$%&(cid:27)(cid:30) )%(cid:30)%)2%(cid:30) (cid:27)(cid:28)% )(cid:29)1(cid:28)(cid:27) (cid:27)! "(cid:28)’&1% !) (cid:31)(cid:29)(cid:30)"!&(cid:27)(cid:29)&#% (cid:27)(cid:28)%(cid:30)% *)!(cid:31)#"(cid:27)(cid:30) /(cid:29)(cid:27)(cid:28)!#(cid:27) &!(cid:27)(cid:29)"%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:16)(cid:19)(cid:1)(cid:20)(cid:21)(cid:20)(cid:22)(cid:18)(cid:23)(cid:13)(cid:2)(cid:14) (cid:24)(cid:13)(cid:21)(cid:18)(cid:1) (cid:25)(cid:20)(cid:21)(cid:5) (cid:1)(cid:6)(cid:5)(cid:26)(cid:20)(cid:21)(cid:21)(cid:23)(cid:21)(cid:15)(cid:20)(cid:24)(cid:24)(cid:18)(cid:15) (cid:20)(cid:2)(cid:16)(cid:12)(cid:21)(cid:1) SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Test VCC Under Test Point Input 50% 50% 0 V CL = 50 pF (see Note A) tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% LOAD CIRCUIT 10% 10% VOL tr tf 90% 90% VCC tPHL tPLH VOH Input 105%0% 501%0% Out-of-Phase 90% 50% 50% 90% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time, with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HC7001D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC7001 & no Sb/Br) SN74HC7001DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC7001 & no Sb/Br) SN74HC7001DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC7001 & no Sb/Br) SN74HC7001DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC7001 & no Sb/Br) SN74HC7001N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC7001N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC7001DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC7001DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC7001DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC7001DT SOIC D 14 250 210.0 185.0 35.0 PackMaterials-Page2

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