(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V (cid:1) ±4-mA Output Drive at 5 V (cid:1) Outputs Can Drive Up To 10 LSTTL Loads (cid:1) Low Input Current of 1 µA Max (cid:1) Low Power Consumption, 80-µA Max I (cid:1) Allow Design of Either RC- or CC (cid:1) Crystal-Oscillator Circuits Typical tpd = 14 ns SN54HC4060...J OR W PACKAGE SN54HC4060...FK PACKAGE SN74HC4060...D, DB, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) M LC CC J Q Q NV Q QL 1 16 VCC QM 2 15 QJ QN 43 2 1 20 1918 QH QN 3 14 QH QF 5 17 QI QF 4 13 QI NC 6 16 NC QE 5 12 CLR QE 7 15 CLR QG 6 11 CLKI QG 8 14 CLKI QD 7 10 CLKO 9 10 1112 13 GND 8 9 CLKO DD C O O Q N N K K G L L C C NC − No internal connection description/ordering information The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and CLKO goes low) and resets the counter to zero (all Q outputs low). ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC4060N SN74HC4060N Tube of 40 SN74HC4060D SSOOIICC −− DD Reel of 2500 SN74HC4060DR HHCC44006600 Reel of 250 SN74HC4060DT −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HC4060NSR HC4060 SSOP − DB Reel of 2000 SN74HC4060DBR HC4060 Tube of 90 SN74HC4060PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC4060PWR HHCC44006600 Reel of 250 SN74HC4060PWT CDIP − J Tube of 25 SNJ54HC4060J SNJ54HC4060J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC4060W SNJ54HC4060W LCCC − FK Tube of 55 SNJ54HC4060FK SNJ54HC4060FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:25)(cid:18)(cid:19)(cid:23)(cid:20)(cid:6)(cid:13)(cid:22)(cid:19)(cid:2) (cid:23)(cid:14)(cid:13)(cid:14) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2003, Texas Instruments Incorporated (cid:25)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:13)&-!# (cid:22)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# (cid:19)(cid:27) ’(cid:30)(cid:29)*%$"# $(cid:29)(cid:31)’)(cid:26)!(cid:27)" "(cid:29) 1(cid:22)(cid:24)(cid:12)(cid:25)(cid:18)2(cid:12)34(cid:3)3(cid:3)(cid:9) !)) ’!(cid:30)!(cid:31)&"&(cid:30)# !(cid:30)& "&#"&* #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:25)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& %(cid:27))&## (cid:29)",&(cid:30).(cid:26)#& (cid:27)(cid:29)"&*+ (cid:19)(cid:27) !)) (cid:29)",&(cid:30) ’(cid:30)(cid:29)*%$"#(cid:9) ’(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS FFUUNNCCTTIIOONN CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) R R R R R R R R R T T T T T T T T T 4 6 14 13 15 1 2 3 QF QG QH QI QJ QL QM QN 12 CLR R R R R R T T T T T 9 11 CLKO CLKI 10 CLKO 7 5 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. QD QE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4060 SN74HC4060 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC4060 SN74HC4060 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 AAllll oouuttppuuttss VVII == VVIIHH oorr VVIILL,, IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH 6 V 5.9 5.999 5.9 5.9 VV IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 QQ oouuttppuuttss VVII == VVIIHH oorr VVIILL IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 AAllll oouuttppuuttss VVII == VVIIHH oorr VVIILL,, IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 QQ oouuttppuuttss VVII == VVIIHH oorr VVIILL IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC4060 SN74HC4060 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 5.5 3.7 4.3 ffcclloocckk CClloocckk ffrreeqquueennccyy 4.5 V 28 19 22 MMHHzz 6 V 33 22 25 2 V 90 135 115 CCLLKKII hhiigghh oorr llooww 4.5 V 18 27 23 6 V 15 23 20 ttww PPuullssee dduurraattiioonn nnss 2 V 90 135 115 CCLLRR hhiigghh 4.5 V 18 27 23 6 V 15 23 20 2 V 160 240 200 ttssuu SSeettuupp ttiimmee,, CCLLRR iinnaaccttiivvee bbeeffoorree CCLLKKII↓↓ 4.5 V 32 48 40 nnss 6 V 27 41 34 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC4060 SN74HC4060 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 5.5 10 3.7 4.3 ffmmaaxx 4.5 V 28 45 19 22 MMHHzz 6 V 33 53 22 25 2 V 240 490 735 615 ttppdd CCLLKKII QQDD 4.5 V 58 98 147 123 nnss 6 V 42 83 125 105 2 V 66 140 210 175 ttPPHHLL CCLLRR AAnnyy QQ 4.5 V 18 28 42 35 nnss 6 V 14 24 36 30 2 V 28 75 110 95 tttt AAnnyy 4.5 V 8 15 22 19 nnss 6 V 6 30 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 88 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Test VCC Reference Under Test Point 50% Input 0 V CL = 50 pF (see Note A) tsu Data VCC 90% 90% LOAD CIRCUIT Input 50% 50% 10% 10% 0 V VCC tr tf Input 50% 50% VOLTAGE WAVEFORMS 0 V SETUP AND INPUT RISE AND FALL TIMES tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% 10% 10% VOL High-Level VCC tr tf Pulse 50% 50% tPHL tPLH 0 V VOH tw Out-of-Phase 90% 50% 50% 90% Output 10% 10% VOL Low-Level VCC tf tr Pulse 50% 50% 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES PULSE DURATIONS NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:7) (cid:11)(cid:4)(cid:12)(cid:1)(cid:13)(cid:14)(cid:15)(cid:16) (cid:14)(cid:1)(cid:17)(cid:2)(cid:6)(cid:5)(cid:18)(cid:19)(cid:2)(cid:19)(cid:20)(cid:1) (cid:21)(cid:22)(cid:2)(cid:14)(cid:18)(cid:17) (cid:6)(cid:19)(cid:20)(cid:2)(cid:13)(cid:16)(cid:18)(cid:1) (cid:14)(cid:2)(cid:23) (cid:19)(cid:1)(cid:6)(cid:22)(cid:24)(cid:24)(cid:14)(cid:13)(cid:19)(cid:18)(cid:1) SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 CONNECTING AN RC-OSCILLATOR CIRCUIT TO THE ’HC4060 DEVICES The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. When an RC-oscillator circuit is implemented, two resistors and a capacitor are required. The components are attached to the terminals as shown: 1 16 2 15 3 14 4 13 5 12 R2 6 11 R1 7 10 C 8 9 To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency (f), use this formula: f(cid:1) (cid:2) 1 (cid:4) 2(R1)(C) 0.405R2(cid:3)0.693 R1(cid:3)R2 If R2 > > R1 (i.e., R2 = 10R1), the above formula simplifies to: f(cid:1)0.455 RC 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN54HC4060FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SN54HC 4060FK SN74HC4060D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060DT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC4060N & no Sb/Br) SN74HC4060NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060NSRE4 ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) SN74HC4060PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC4060 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC4060, SN74HC4060 : •Catalog: SN74HC4060 •Automotive: SN74HC4060-Q1, SN74HC4060-Q1 •Military: SN54HC4060 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC4060DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC4060NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC4060PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4060PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4060PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4060PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC4060DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC4060NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC4060PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HC4060PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC4060PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC4060PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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