(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V (cid:1) ±6-mA Output Drive at 5 V (cid:1) High-Current 3-State True Outputs Can (cid:1) Low Input Current of 1 µA Max Drive Up To 15 LSTTL Loads (cid:1) Eight High-Current Latches in a Single (cid:1) Low Power Consumption, 80-µA Max I Package CC (cid:1) (cid:1) Typical tpd = 13 ns Full Parallel Access for Loading SN54HC373...J OR W PACKAGE SN54HC373...FK PACKAGE SN74HC373...DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) C D Q E CQ 1 1 O V 8 OE 1 20 VCC 1Q 2 19 8Q 3 2 1 20 19 2D 4 18 8D 1D 3 18 8D 2Q 5 17 7D 2D 4 17 7D 3Q 6 16 7Q 2Q 5 16 7Q 3D 7 15 6Q 3Q 6 15 6Q 4D 8 14 6D 3D 7 14 6D 9 10 1112 13 4D 8 13 5D QD EQ D 4Q 9 12 5Q 4N L5 5 G GND 10 11 LE description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 20 SN74HC373N SN74HC373N Tube of 25 SN74HC373DW SSOOIICC −− DDWW HHCC337733 Reel of 2000 SN74HC373DWR SOP − NS Reel of 2000 SN74HC373NSR HC373 −−4400°°CC ttoo 8855°°CC SSOP − DB Reel of 2000 SN74HC373DBR HC373 Tube of 70 SN74HC373PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC373PWR HHCC337733 Reel of 250 SN74HC373PWT CDIP − J Tube of 20 SNJ54HC373J SNJ54HC373J −−5555°CC ttoo 112255°CC CFP − W Tube of 85 SNJ54HC373W SNJ54HC373W LCCC − FK Tube of 55 SNJ54HC373FK SNJ54HC373FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:15)(cid:14)(cid:10)(cid:17)(cid:22)(cid:6)(cid:11)(cid:21)(cid:10)(cid:2) (cid:17)(cid:12)(cid:11)(cid:12) (cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) (cid:23)(cid:31) !"(cid:27)(cid:27)#(cid:24)(cid:30) (cid:29)(cid:31) (cid:26)(cid:25) $"%&(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) ’(cid:29)(cid:30)#( Copyright  2003, Texas Instruments Incorporated (cid:15)(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28) (cid:30)(cid:26) (cid:31)$#!(cid:23)(cid:25)(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24)(cid:31) $#(cid:27) (cid:30))# (cid:30)#(cid:27)(cid:28)(cid:31) (cid:26)(cid:25) (cid:11)#*(cid:29)(cid:31) (cid:21)(cid:24)(cid:31)(cid:30)(cid:27)"(cid:28)#(cid:24)(cid:30)(cid:31) (cid:10)(cid:24) $(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:28)$&(cid:23)(cid:29)(cid:24)(cid:30) (cid:30)(cid:26) .(cid:21)(cid:13)(cid:18)(cid:15)(cid:14)/(cid:18)(cid:7)0(cid:3)(cid:7)(cid:3)(cid:9) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31) (cid:29)(cid:27)# (cid:30)#(cid:31)(cid:30)#’ (cid:31)(cid:30)(cid:29)(cid:24)’(cid:29)(cid:27)’ +(cid:29)(cid:27)(cid:27)(cid:29)(cid:24)(cid:30),( (cid:15)(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# "(cid:24)&#(cid:31)(cid:31) (cid:26)(cid:30))#(cid:27)+(cid:23)(cid:31)# (cid:24)(cid:26)(cid:30)#’( (cid:10)(cid:24) (cid:29)&& (cid:26)(cid:30))#(cid:27) $(cid:27)(cid:26)’"!(cid:30)(cid:31)(cid:9) $(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 description/ordering information (continued) An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. FUNCTION TABLE (each latch) INPUTS OOUUTTPPUUTT OE LE D Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1 OE 11 LE C1 2 3 1Q 1D 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC373 SN74HC373 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC373 SN74HC373 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC373 SN74HC373 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 80 120 100 ttww PPuullssee dduurraattiioonn,, LLEE hhiigghh 4.5 V 16 24 20 nnss 6 V 14 20 17 2 V 50 75 63 ttssuu SSeettuupp ttiimmee,, ddaattaa bbeeffoorree LLEE↓↓ 4.5 V 10 15 13 nnss 6 V 9 13 11 2 V 20 26 24 tthh HHoolldd ttiimmee,, ddaattaa aafftteerr LLEE↓↓ 4.5 V 10 13 12 nnss 6 V 10 13 12 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC373 SN74HC373 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 58 150 225 190 DD QQ 4.5 V 15 30 45 38 6 V 13 26 38 32 ttppdd nnss 2 V 73 175 265 220 LLEE AAnnyy QQ 4.5 V 18 35 53 44 6 V 15 30 45 38 2 V 65 150 225 190 tteenn OOEE AAnnyy QQ 4.5 V 17 30 45 38 nnss 6 V 14 26 38 32 2 V 50 150 225 190 ttddiiss OOEE AAnnyy QQ 4.5 V 15 30 45 38 nnss 6 V 13 26 38 32 2 V 28 60 90 75 tttt AAnnyy QQ 4.5 V 8 12 18 15 nnss 6 V 6 10 15 13 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC373 SN74HC373 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 82 200 300 250 DD QQ 4.5 V 22 40 60 50 6 V 19 34 51 43 ttppdd nnss 2 V 100 225 335 285 LLEE AAnnyy QQ 4.5 V 24 45 67 57 6 V 20 38 57 48 2 V 90 200 300 250 tteenn OOEE AAnnyy QQ 4.5 V 23 40 60 50 nnss 6 V 19 34 51 43 2 V 45 210 315 265 tttt AAnnyy QQ 4.5 V 17 42 63 53 nnss 6 V 13 36 53 45 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per latch No load 100 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:10)(cid:6)(cid:11)(cid:12)(cid:13) (cid:11)(cid:14)(cid:12)(cid:2)(cid:1)(cid:15)(cid:12)(cid:14)(cid:16)(cid:2)(cid:11) (cid:17)(cid:18)(cid:11)(cid:19)(cid:15)(cid:16) (cid:13)(cid:12)(cid:11)(cid:6)(cid:5)(cid:16)(cid:1) (cid:20)(cid:21)(cid:11)(cid:5) (cid:7)(cid:18)(cid:1)(cid:11)(cid:12)(cid:11)(cid:16) (cid:10)(cid:22)(cid:11)(cid:15)(cid:22)(cid:11)(cid:1) SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 S1 tPZH 50 pF Open Closed Test ten 1 kΩ or From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL tdis 1 kΩ 50 pF (see Note A) S2 tPLZ Closed Open 50 pF tpd or tt −− or Open Open 150 pF LOAD CIRCUIT VCC Reference 50% Input High-Level VCC 0 V 50% 50% Pulse tsu th 0 V tw Data 90% 90% VCC Input 50% 50% Low-Level VCC 10% 10% 0 V Pulse 50% 50% tr tf 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC Output VCC Input 50% 50% Control 50% 50% (Low-Level 0 V Enabling) 0 V tPLH tPHL tPZL tPLZ In-Phase 90% 90% VOH Output ≈VCC ≈VCC Output 50% 50% Waveform 1 50% 10% tr 10%tfVOL (See Note B) 10% VOL tPHL tPLH tPZH tPHZ Out-of- 90% 50% 50% 90% VOH Output 90% VOH Waveform 2 50% Phase 10% 10% VOL (See Note B) ≈0 V Output tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8407201VRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8407201VR A SNV54HC373J 5962-8407201VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8407201VS A SNV54HC373W 84072012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84072012A SNJ54HC 373FK 8407201RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201RA SNJ54HC373J 8407201SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201SA SNJ54HC373W JM38510/65403B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65403B2A JM38510/65403BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65403BRA M38510/65403B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65403B2A M38510/65403BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 65403BRA SN54HC373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HC373J SN74HC373DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N (RoHS) SN74HC373NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N (RoHS) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HC373NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373NSRE4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SN74HC373PWT ACTIVE TSSOP PW 20 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 & no Sb/Br) SNJ54HC373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84072012A SNJ54HC 373FK SNJ54HC373J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201RA SNJ54HC373J SNJ54HC373W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201SA SNJ54HC373W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC373, SN54HC373-SP, SN74HC373 : •Catalog: SN74HC373, SN54HC373 •Military: SN54HC373 •Space: SN54HC373-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HC373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74HC373NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74HC373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 SN74HC373PWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC373DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74HC373DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HC373NSR SO NS 20 2000 367.0 367.0 45.0 SN74HC373PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HC373PWT TSSOP PW 20 250 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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