(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3) (cid:5)(cid:11)(cid:12) (cid:13)(cid:14)(cid:15)(cid:15)(cid:11)(cid:16)(cid:1) (cid:17)(cid:2)(cid:18) (cid:19)(cid:20)(cid:2)(cid:11) (cid:18)(cid:16)(cid:20)(cid:21)(cid:11)(cid:16)(cid:1) (cid:22)(cid:20)(cid:23)(cid:5) (cid:7)(cid:24)(cid:1)(cid:23)(cid:17)(cid:23)(cid:11) (cid:25)(cid:14)(cid:23)(cid:26)(cid:14)(cid:23)(cid:1) SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V SN54HC365...J OR W PACKAGE (cid:1) SN74HC365...D, N, NS, OR PW PACKAGE High-Current 3-State Outputs Drive Bus (TOP VIEW) Lines, Buffer-Memory Address Registers, or Drive Up To 15 LSTTL Loads OE1 1 16 VCC (cid:1) True Outputs A1 2 15 OE2 (cid:1) Low Power Consumption, 80-µA Max I Y1 3 14 A6 CC (cid:1) A2 4 13 Y6 Typical tpd = 10 ns (cid:1) ±6-mA Output Drive at 5 V Y2 5 12 A5 A3 6 11 Y5 (cid:1) Low Input Current of 1 µA Max Y3 7 10 A4 GND 8 9 Y4 description/ordering information These hex buffers and line drivers are designed SN54HC365...FK PACKAGE specifically to improve both the performance and (TOP VIEW) density of 3-state memory address drivers, clock 1 C2 drivers, and bus-oriented receivers and A1 OE NC VCOE transmitters. The ’HC365 devices contain six independent buffers/drivers with dual-gated Y1 43 2 1 20 1918 A6 output-enable (OE1 and OE2) inputs. When OE1 A2 5 17 Y6 and OE2 are both low, the devices pass NC 6 16 NC noninverted data from the A inputs to the Y2 7 15 A5 Y outputs. If either (or both) output-enable A3 8 14 Y5 terminal(s) is high, the outputs are in the 9 10 1112 13 high-impedance state. 3D C4 4 YN NY A G NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC365N SN74HC365N Tube of 40 SN74HC365D SSOOIICC −− DD Reel of 2500 SN74HC365DR HHCC336655 Reel of 250 SN74HC365DT −−4400°°CC ttoo 8855°°CC SOP − NS Reel of 2000 SN74HC365NSR HC365 Reel of 90 SN74HC365PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC365PWR HHCC336655 Reel of 250 SN74HC365PWT CDIP − J Tube of 25 SNJ54HC365J SNJ54HC365J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC365W SNJ54HC365W LCCC − FK Tube of 55 SNJ54HC365FK SNJ54HC365FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:26)(cid:16)(cid:25)(cid:18)(cid:14)(cid:6)(cid:23)(cid:20)(cid:25)(cid:2) (cid:18)(cid:17)(cid:23)(cid:17) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  2003, Texas Instruments Incorporated (cid:26)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:23)’."$ (cid:20)(cid:28)$#(cid:31)&!’(cid:28)#$ (cid:25)(cid:28) ((cid:31)(cid:30)+&%#$ %(cid:30)!(*(cid:27)"(cid:28)# #(cid:30) 2(cid:20)(cid:19)(cid:24)(cid:26)(cid:16)(cid:15)(cid:24)(cid:7)3(cid:3)(cid:7)(cid:3)(cid:9) "** ("(cid:31)"!’#’(cid:31)$ "(cid:31)’ #’$#’+ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:26)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ &(cid:28)*’$$ (cid:30)#-’(cid:31)/(cid:27)$’ (cid:28)(cid:30)#’+, (cid:25)(cid:28) "** (cid:30)#-’(cid:31) ((cid:31)(cid:30)+&%#$(cid:9) ((cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3) (cid:5)(cid:11)(cid:12) (cid:13)(cid:14)(cid:15)(cid:15)(cid:11)(cid:16)(cid:1) (cid:17)(cid:2)(cid:18) (cid:19)(cid:20)(cid:2)(cid:11) (cid:18)(cid:16)(cid:20)(cid:21)(cid:11)(cid:16)(cid:1) (cid:22)(cid:20)(cid:23)(cid:5) (cid:7)(cid:24)(cid:1)(cid:23)(cid:17)(cid:23)(cid:11) (cid:25)(cid:14)(cid:23)(cid:26)(cid:14)(cid:23)(cid:1) SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003 FUNCTION TABLE (each buffer/driver) INPUTS OOUUTTPPUUTT OE1 OE2 A Y H X X Z X H X Z L L H H L L L L logic diagram (positive logic) 1 OE1 15 OE2 2 3 A1 Y1 To Five Other Channels Pin numbers shown are for the D, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3) (cid:5)(cid:11)(cid:12) (cid:13)(cid:14)(cid:15)(cid:15)(cid:11)(cid:16)(cid:1) (cid:17)(cid:2)(cid:18) (cid:19)(cid:20)(cid:2)(cid:11) (cid:18)(cid:16)(cid:20)(cid:21)(cid:11)(cid:16)(cid:1) (cid:22)(cid:20)(cid:23)(cid:5) (cid:7)(cid:24)(cid:1)(cid:23)(cid:17)(cid:23)(cid:11) (cid:25)(cid:14)(cid:23)(cid:26)(cid:14)(cid:23)(cid:1) SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54HC365 SN74HC365 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC365 SN74HC365 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3) (cid:5)(cid:11)(cid:12) (cid:13)(cid:14)(cid:15)(cid:15)(cid:11)(cid:16)(cid:1) (cid:17)(cid:2)(cid:18) (cid:19)(cid:20)(cid:2)(cid:11) (cid:18)(cid:16)(cid:20)(cid:21)(cid:11)(cid:16)(cid:1) (cid:22)(cid:20)(cid:23)(cid:5) (cid:7)(cid:24)(cid:1)(cid:23)(cid:17)(cid:23)(cid:11) (cid:25)(cid:14)(cid:23)(cid:26)(cid:14)(cid:23)(cid:1) SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC365 SN74HC365 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 50 95 145 120 ttppdd AA YY 4.5 V 12 19 29 24 nnss 6 V 10 16 25 20 2 V 100 190 285 238 tteenn OOEE YY 4.5 V 26 38 57 48 nnss 6 V 21 32 48 41 2 V 50 175 265 240 ttddiiss OOEE YY 4.5 V 21 35 53 48 nnss 6 V 19 30 45 41 2 V 28 60 90 75 tttt AAnnyy 4.5 V 8 12 18 15 nnss 6 V 6 10 15 13 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC365 SN74HC365 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 70 120 180 150 ttppdd AA YY 4.5 V 17 24 36 30 nnss 6 V 14 20 31 25 2 V 140 230 345 285 tteenn OOEE YY 4.5 V 30 46 69 57 nnss 6 V 28 39 59 48 2 V 45 210 315 265 tttt AAnnyy 4.5 V 17 42 63 53 nnss 6 V 13 36 53 45 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per buffer/driver No load 35 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3) (cid:5)(cid:11)(cid:12) (cid:13)(cid:14)(cid:15)(cid:15)(cid:11)(cid:16)(cid:1) (cid:17)(cid:2)(cid:18) (cid:19)(cid:20)(cid:2)(cid:11) (cid:18)(cid:16)(cid:20)(cid:21)(cid:11)(cid:16)(cid:1) (cid:22)(cid:20)(cid:23)(cid:5) (cid:7)(cid:24)(cid:1)(cid:23)(cid:17)(cid:23)(cid:11) (cid:25)(cid:14)(cid:23)(cid:26)(cid:14)(cid:23)(cid:1) SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 S1 tPZH 50 pF Open Closed Test ten 1 kΩ or From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL S2 tdis tPLZ 1 kΩ 50 pF Closed Open (see Note A) 50 pF tpd or tt −− or Open Open 150 pF LOAD CIRCUIT VCC Input 50% 50% 0 V tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% 10% 10% VOL tr tf Output tPHL tPLH Control VCC VOH (Low-Level 50% 50% Out-of-Phase 90% 50% 50% 90% Enabling) 0 V Output 10% 10% VOL tPZL tPLZ tf tr Output ≈VCC ≈VCC Waveform 1 50% VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES (See Note B) 10% VOL tPZH tPHZ VCC Output VOH 90% 90% 90% Input 50% 50% Waveform 2 50% 10% 10% 0 V (See Note B) ≈0 V tr tf VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 8500101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8500101EA SNJ54HC365J JM38510/65706BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65706BEA M38510/65706BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65706BEA SN54HC365J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC365J SN74HC365D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365DRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC365N & no Sb/Br) SN74HC365NE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC365N & no Sb/Br) SN74HC365NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SN74HC365PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC365 & no Sb/Br) SNJ54HC365J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8500101EA SNJ54HC365J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC365, SN74HC365 : •Catalog: SN74HC365 •Military: SN54HC365 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC365DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC365PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC365PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC365DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC365PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC365PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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