(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V SN54HC259...J OR W PACKAGE (cid:1) SN74HC259...D, N, NS, OR PW PACKAGE High-Current Inverting Outputs Drive Up To (TOP VIEW) 10 LSTTL Loads (cid:1) Low Power Consumption, 80-µA Max I CC S0 1 16 VCC (cid:1) Typical tpd = 14 ns S1 2 15 CLR (cid:1) ±4-mA Output Drive at 5 V S2 3 14 G (cid:1) Low Input Current of 1 µA Max Q0 4 13 D (cid:1) Q1 5 12 Q7 8-Bit Parallel-Out Storage Register Q2 6 11 Q6 Performs Serial-to-Parallel Conversion With Q3 7 10 Q5 Storage GND 8 9 Q4 (cid:1) Asynchronous Parallel Clear (cid:1) Active-High Decoder SN54HC259...FK PACKAGE (cid:1) (TOP VIEW) Enable Input Simplifies Expansion (cid:1) Expandable for n-Bit Applications 1 0 C CCLR (cid:1) S S N V C Four Distinct Functional Modes 3 2 1 2019 description/ordering information S2 4 18 G Q0 5 17 D These 8-bit addressable latches are designed for NC 6 16 NC general-purpose storage applications in digital Q1 7 15 Q7 systems. Specific uses include working registers, Q2 8 14 Q6 9 10 11 12 13 serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional 3 D C 45 Q N N QQ devices capable of storing single-line data in eight G addressable latches and being a 1-of-8 decoder NC − No internal connection or demultiplexer with active-high outputs. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC259N SN74HC259N Tube of 40 SN74HC259D SSOOIICC −− DD Reel of 2500 SN74HC259DR HHCC225599 −−4400°CC ttoo 8855°CC Reel of 250 SN74HC259DT SOP − NS Reel of 2000 SN74HC259NSR HC259 Reel of 2000 SN74HC259PWR TTSSSSOOPP −− PPWW HHCC225599 Reel of 250 SN74HC259PWT CDIP − J Tube of 25 SNJ54HC259J SNJ54HC259J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC259W SNJ54HC259W LCCC − FK Tube of 55 SNJ54HC259FK SNJ54HC259FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:21)(cid:18)(cid:22)(cid:17)(cid:23)(cid:6)(cid:15)(cid:14)(cid:22)(cid:2) (cid:17)(cid:16)(cid:15)(cid:16) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2003, Texas Instruments Incorporated (cid:21)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:15)$+(cid:30)! (cid:14)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! (cid:22)(cid:25) %(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:29)%’(cid:24)(cid:30)(cid:25)(cid:31) (cid:31)(cid:27) /(cid:14)(cid:20)(cid:12)(cid:21)(cid:18)0(cid:12)1(cid:11)(cid:3)1(cid:3)(cid:9) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)! (cid:30)(cid:28)$ (cid:31)$!(cid:31)$( !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:21)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ #(cid:25)’$!! (cid:27)(cid:31)*$(cid:28),(cid:24)!$ (cid:25)(cid:27)(cid:31)$() (cid:22)(cid:25) (cid:30)’’ (cid:27)(cid:31)*$(cid:28) %(cid:28)(cid:27)(#"(cid:31)!(cid:9) %(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. Function Tables FUNCTION INPUTS OUTPUT OF EACH AADDDDRREESSSSEEDD OOTTHHEERR FFUUNNCCTTIIOONN CLR G LATCH OUTPUT H L D QiO Addressable latch H H QiO QiO Memory L L D L 8-line demultiplexer L H L L Clear LATCH SELECTION SELECT INPUTS LLAATTCCHH S2 S1 S0 ADDRESSED L L L 0 L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 logic diagram D 1 4 S0 C Q Q0 R D 5 C Q Q1 R D 2 6 S1 C Q Q2 R D 7 C Q Q3 R 3 S2 D 9 C Q Q4 R D 10 C Q Q5 R 14 G D 11 C Q Q6 R 13 D D 12 C Q Q7 R 15 CLR Pin numbers shown are for the D, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 logic diagram, each internal latch (positive logic) C D TG Q C C C C C TG R C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC259 SN74HC259 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC259 SN74HC259 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC259 SN74HC259 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 80 120 100 CCLLRR llooww 4.5 V 16 24 20 6 V 14 20 17 ttww PPuullssee dduurraattiioonn nnss 2 V 80 120 100 GG llooww 4.5 V 16 24 20 6 V 14 20 17 2 V 75 115 95 ttssuu SSeettuupp ttiimmee,, ddaattaa oorr aaddddrreessss bbeeffoorree GG↑↑ 4.5 V 15 23 19 nnss 6 V 13 20 16 2 V 5 5 5 tthh HHoolldd ttiimmee,, ddaattaa oorr aaddddrreessss aafftteerr GG↑ 4.5 V 5 5 5 nnss 6 V 5 5 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC259 SN74HC259 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 60 150 225 190 ttPPHHLL CCLLRR AAnnyy QQ 4.5 V 18 30 45 38 nnss 6 V 14 26 38 32 2 V 56 130 195 165 DDaattaa AAnnyy QQ 4.5 V 17 26 39 33 6 V 13 22 33 28 2 V 74 200 300 250 ttppdd AAddddrreessss AAnnyy QQ 4.5 V 21 40 60 50 nnss 6 V 17 34 51 43 2 V 66 170 255 215 GG AAnnyy QQ 4.5 V 20 34 51 43 6 V 16 29 43 37 2 V 28 75 110 95 tttt AAnnyy 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per latch No load 33 pF 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:1)(cid:16)(cid:13)(cid:20)(cid:19) (cid:20)(cid:16)(cid:15)(cid:6)(cid:5)(cid:19)(cid:1) SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC High-Level 50% 50% Pulse From Output Test 0 V Under Test Point tw CL = 50 pF VCC (see Note A) Low-Level 50% 50% Pulse 0 V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0 V tPLH tPHL ReferIennpcuet 50% VCC InO-Puhtapsuet 105%0% 90% 90% 501%0% VOH 0 V VOL tsu th tr tf tPHL tPLH Data VCC VOH Input 50% 90% 90% 50% Out-of-Phase 90% 50% 50% 90% 10% 10% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 85519012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85519012A SNJ54HC 259FK 8551901EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8551901EA SNJ54HC259J JM38510/65402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65402BEA M38510/65402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65402BEA SN54HC259J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC259J SN74HC259D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259DG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259DRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259DRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259DT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N & no Sb/Br) SN74HC259NE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N & no Sb/Br) SN74HC259NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SN74HC259PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259 & no Sb/Br) SNJ54HC259FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85519012A SNJ54HC Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 259FK SNJ54HC259J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8551901EA SNJ54HC259J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC259, SN74HC259 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 •Catalog: SN74HC259 •Military: SN54HC259 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC259DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC259DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC259DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC259DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC259NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC259PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC259DR SOIC D 16 2500 367.0 367.0 38.0 SN74HC259DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC259DR SOIC D 16 2500 364.0 364.0 27.0 SN74HC259DRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74HC259NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC259PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HC259PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC259PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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