(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 (cid:1) 3-State Version of ’HC151 SN54HC251...J OR W PACKAGE (cid:1) SN74HC251...D, DB, N, NS, OR PW PACKAGE Wide Operating Voltage Range of 2 V to 6 V (TOP VIEW) (cid:1) High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up D3 1 16 V CC To 15 LSTTL Loads D2 2 15 D4 (cid:1) Low Power Consumption, 80-µA Max ICC D1 3 14 D5 (cid:1) Typical tpd = 9 ns D0 4 13 D6 (cid:1) ±6-mA Output Drive at 5 V Y 5 12 D7 (cid:1) Low Input Current of 1 µA Max W 6 11 A OE 7 10 B (cid:1) Perform Parallel-to-Serial Conversion GND 8 9 C (cid:1) Complementary Outputs Provide True and Inverted Data SN54HC251...FK PACKAGE (TOP VIEW) description/ordering information C 23 C C4 These data selectors/multiplexers contain full DD N V D binary decoding to select 1-of-8 data sources and 3 2 1 2019 feature strobe-controlled complementary 3-state D1 4 18 D5 outputs. D0 5 17 D6 The 3-state outputs can interface with and drive NC 6 16 NC data lines of bus-organized systems. With all but Y 7 15 D7 one of the common outputs disabled (in the W 8 14 A 9 10 11 12 13 high-impedance state), the low impedance of the single enabled output drives the bus line to a high E D C CB O N N or low logic level. Both outputs are controlled by G the output-enable (OE) input. The outputs are NC − No internal connection disabled when OE is high. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC251N SN74HC251N Tube of 40 SN74HC251D SSOOIICC −− DD Reel of 2500 SN74HC251DR HHCC225511 Reel of 250 SN74HC251DT −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HC251NSR HC251 SSOP − DB Reel of 2000 SN74HC251DBR HC251 Tube of 90 SN74HC251PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC251PWR HHCC225511 Reel of 250 SN74HC251PWT CDIP − J Tube of 25 SNJ54HC251J SNJ54HC251J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC251W SNJ54HC251W LCCC − FK Tube of 55 SNJ54HC251FK SNJ54HC251FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:22)(cid:17)(cid:16)(cid:11)(cid:20)(cid:6)(cid:13)(cid:21)(cid:16)(cid:2) (cid:11)(cid:12)(cid:13)(cid:12) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  2003, Texas Instruments Incorporated (cid:22)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:13)’."$ (cid:21)(cid:28)$#(cid:31)&!’(cid:28)#$ (cid:16)(cid:28) ((cid:31)(cid:30)+&%#$ %(cid:30)!(*(cid:27)"(cid:28)# #(cid:30) (cid:19)(cid:21)(cid:15)(cid:26)(cid:22)(cid:17)2(cid:26)(cid:25)3(cid:3)(cid:25)(cid:3)(cid:9) "** ("(cid:31)"!’#’(cid:31)$ "(cid:31)’ #’$#’+ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:22)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ &(cid:28)*’$$ (cid:30)#-’(cid:31)/(cid:27)$’ (cid:28)(cid:30)#’+, (cid:16)(cid:28) "** (cid:30)#-’(cid:31) ((cid:31)(cid:30)+&%#$(cid:9) ((cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE INPUTS OUTPUTS SELECT OOEE YY WW C B A X X X H Z Z L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 D0, D1...D7 = the level of the respective D input 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 7 OE 11 A 10 B 9 C 4 D0 TG 3 D1 TG 2 D2 TG 5 Y 1 D3 TG 15 D4 TG 6 W 14 D5 TG 13 D6 TG 12 D7 TG Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC251 SN74HC251 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC251 SN74HC251 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0, VI = VIH or VIL 6 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC251 SN74HC251 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 58 205 300 256 AA,, BB,, oorr CC WW oorr YY 4.5 V 21 41 60 51 6 V 19 35 51 44 ttppdd nnss 2 V 44 195 283 244 AAnnyy DD WW oorr YY 4.5 V 17 39 57 49 6 V 15 33 48 41 2 V 30 145 210 181 tteenn OOEE WW oorr YY 4.5 V 10 29 42 36 nnss 6 V 9 25 36 31 2 V 25 195 283 244 ttddiiss OOEE WW oorr YY 4.5 V 15 39 57 49 nnss 6 V 14 33 48 41 2 V 20 75 110 95 tttt WW oorr YY 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC251 SN74HC251 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 72 300 450 375 AA,, BB,, oorr CC WW oorr YY 4.5 V 25 60 90 75 6 V 22 52 77 65 ttppdd nnss 2 V 59 300 450 375 AAnnyy DD WW oorr YY 4.5 V 21 60 90 75 6 V 18 52 77 65 2 V 50 230 340 285 tteenn OOEE WW oorr YY 4.5 V 17 46 68 57 nnss 6 V 15 40 58 50 2 V 45 210 315 265 tttt WW oorr YY 4.5 V 17 42 63 53 nnss 6 V 13 36 53 45 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 70 pF 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:3)(cid:8) (cid:11)(cid:12)(cid:13)(cid:12) (cid:1)(cid:14)(cid:15)(cid:14)(cid:6)(cid:13)(cid:16)(cid:17)(cid:1)(cid:18)(cid:19)(cid:20)(cid:15)(cid:13)(cid:21)(cid:22)(cid:15)(cid:14)(cid:23)(cid:14)(cid:17)(cid:1) (cid:24)(cid:21)(cid:13)(cid:5) (cid:25)(cid:26)(cid:1)(cid:13)(cid:12)(cid:13)(cid:14) (cid:16)(cid:20)(cid:13)(cid:22)(cid:20)(cid:13)(cid:1) SCLS132E − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 S1 tPZH 50 pF Open Closed Test ten 1 kΩ or From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL S2 tdis tPLZ 1 kΩ 50 pF Closed Open (see Note A) 50 pF tpd or tt −− or Open Open 150 pF LOAD CIRCUIT VCC Input 50% 50% 0 V tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% 10% 10% VOL tr tf Output tPHL tPLH Control VCC VOH (Low-Level 50% 50% Out-of-Phase 90% 50% 50% 90% Enabling) 0 V Output 10% 10% VOL tPZL tPLZ tf tr Output ≈VCC ≈VCC VOLTAGE WAVEFORMS Waveform 1 50% PROPAGATION DELAY AND OUTPUT TRANSITION TIMES (See Note B) 10% VOL tPZH tPHZ VCC Output VOH 90% 90% 90% Input 50% 50% Waveform 2 50% 10% 10% 0 V (See Note B) ≈0 V tr tf VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 85125012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85125012A SNJ54HC 251FK 8512501EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8512501EA SNJ54HC251J SN54HC251J ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54HC251J SN74HC251D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251DE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251DT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC251N & no Sb/Br) SN74HC251NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SN74HC251PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC251 & no Sb/Br) SNJ54HC251FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85125012A SNJ54HC 251FK Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SNJ54HC251J ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 8512501EA SNJ54HC251J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC251, SN74HC251 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 •Catalog: SN74HC251 •Military: SN54HC251 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC251DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC251NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC251PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC251PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC251DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC251NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC251PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC251PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

None

None

None

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated