(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V (cid:1) Low Input Current of 1 µA Max (cid:1) (cid:1) Outputs Can Drive Up To 10 LSTTL Loads Synchronous Load (cid:1) Low Power Consumption, 80-µA Max I (cid:1) Direct Overriding Clear CC (cid:1) (cid:1) Typical tpd = 13 ns Parallel-to-Serial Conversion (cid:1) ±4-mA Output Drive at 5 V SN54HC166...J OR W PACKAGE SN54HC166...FK PACKAGE SN74HC166...D, DB, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) D ER C CCH/L SER 1 16 VCC A S N V S A 2 15 SH/LD 3 2 1 20 19 B 3 14 H B 4 18 H C 4 13 QH C 5 17 QH D 5 12 G NC 6 16 NC CLK INH 6 11 F D 7 15 G CLK 7 10 E CLK INH 8 14 F 9 10 1112 13 GND 8 9 CLR KD C RE LN N L CG C NC − No internal connection description/ordering information ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC166N SN74HC166N Tube of 40 SN74HC166D SSOOIICC −− DD Reel of 2500 SN74HC166DR HHCC116666 Reel of 250 SN74HC166DT −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HC166NSR HC166 SSOP − DB Reel of 2000 SN74HC166DBR HC166 Tube of 90 SN74HC166PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC166PWR HHCC116666 Reel of 250 SN74HC166PWT CDIP − J Tube of 25 SNJ54HC166J SNJ54HC166J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC166W SNJ54HC166W LCCC − FK Tube of 55 SNJ54HC166FK SNJ54HC166FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:16)(cid:18)(cid:21)(cid:22)(cid:25)(cid:6)(cid:15)(cid:14)(cid:21)(cid:2) (cid:22)(cid:17)(cid:15)(cid:17) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2003, Texas Instruments Incorporated (cid:16)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:15)&-!# (cid:14)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# (cid:21)(cid:27) ’(cid:30)(cid:29)*%$"# $(cid:29)(cid:31)’)(cid:26)!(cid:27)" "(cid:29) 1(cid:14)(cid:19)(cid:12)(cid:16)(cid:18)(cid:23)(cid:12)2(cid:11)(cid:3)2(cid:3)(cid:9) !)) ’!(cid:30)!(cid:31)&"&(cid:30)# !(cid:30)& "&#"&* #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:16)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& %(cid:27))&## (cid:29)",&(cid:30).(cid:26)#& (cid:27)(cid:29)"&*+ (cid:21)(cid:27) !)) (cid:29)",&(cid:30) ’(cid:30)(cid:29)*%$"#(cid:9) ’(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. FUNCTION TABLE OUTPUTS IINNPPUUTTSS INTERNAL PARALLEL QH CLR SH/LD CLK INH CLK SER A...H QA QB L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L ↑ X a...h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 logic diagram (positive logic) A B C D E F G H 2 3 4 5 10 11 12 14 15 SH/LD 1 SER 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 6 R R R R R R R R CLK INH 7 CLK 9 CLR 13 QH Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 typical clear, shift, load, inhibit, and shift sequence CLK CLK INH CLR SER SH/LD A H B L C H D L Parallel Inputs E H F L G H H H QH H H L H L H L H Inhibit Serial Shift Serial Shift Clear Load absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC166 SN74HC166 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv†† IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. †If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC166 SN74HC166 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC166 SN74HC166 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 6 4.2 5 ffcclloocckk CClloocckk ffrreeqquueennccyy 4.5 V 31 21 25 MMHHzz 6 V 36 25 29 2 V 100 150 125 CCLLRR llooww 4.5 V 20 30 25 6 V 17 26 21 ttww PPuullssee dduurraattiioonn nnss 2 V 80 120 100 CCLLKK hhiigghh oorr llooww 4.5 V 16 24 20 6 V 14 20 17 2 V 145 220 180 SSHH//LLDD hhiigghh bbeeffoorree CCLLKK↑↑ 4.5 V 29 44 36 6 V 25 38 31 2 V 80 120 100 SSEERR bbeeffoorree CCLLKK↑↑ 4.5 V 16 24 20 6 V 14 20 17 2 V 100 150 125 ttssuu SSeettuupp ttiimmee CCLLKK IINNHH llooww bbeeffoorree CCLLKK↑↑ 4.5 V 20 30 25 nnss 6 V 17 26 21 2 V 80 120 100 DDaattaa bbeeffoorree CCLLKK↑↑ 4.5 V 16 24 20 6 V 14 20 17 2 V 40 60 50 CCLLRR iinnaaccttiivvee bbeeffoorree CCLLKK↑↑ 4.5 V 8 12 10 6 V 7 10 9 2 V 0 0 0 SSHH//LLDD hhiigghh aafftteerr CCLLKK↑↑ 4.5 V 0 0 0 6 V 0 0 0 2 V 5 5 5 SSEERR aafftteerr CCLLKK↑ 4.5 V 5 5 5 6 V 5 5 5 tthh HHoolldd ttiimmee nnss 2 V 0 0 0 CCLLKK IINNHH hhiigghh aafftteerr CCLLKK↑↑ 4.5 V 0 0 0 6 V 0 0 0 2 V 5 5 5 DDaattaa aafftteerr CCLLKK↑ 4.5 V 5 5 5 6 V 5 5 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC166 SN74HC166 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 6 11 4.2 5 ffmmaaxx 4.5 V 31 36 21 25 MMHHzz 6 V 36 45 25 29 2 V 62 120 180 150 ttPPHHLL CCLLRR QQHH 4.5 V 18 24 36 30 nnss 6 V 13 20 31 26 2 V 75 150 225 190 ttppdd CCLLKK QQHH 4.5 V 15 30 45 38 nnss 6 V 13 26 38 32 2 V 38 75 110 95 tttt AAnnyy 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 50 pF 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:17)(cid:19)(cid:19)(cid:20)(cid:19)(cid:12)(cid:19)(cid:21)(cid:17)(cid:22) (cid:1)(cid:5)(cid:14)(cid:23)(cid:15) (cid:18)(cid:20)(cid:24)(cid:14)(cid:1)(cid:15)(cid:20)(cid:18)(cid:1) SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC High-Level 50% 50% Pulse From Output Test 0 V Under Test Point tw CL = 50 pF Low-Level VCC (see Note A) Pulse 50% 50% 0 V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0 V tPLH tPHL ReferIennpcuet 50% VCC InO-Puhtapsuet 105%0% 90% 90% 501%0% VOH 0 V VOL tsu th tr tf tPHL tPLH Data VCC VOH Input 50% 90% 90% 50% Out-of-Phase 90% 50% 50% 90% 10% 10% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 5962-9050101Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N/AforPkgType 5962-9050101QEA ACTIVE CDIP J 16 1 TBD A42 N/AforPkgType 5962-9050101VEA ACTIVE CDIP J 16 1 TBD A42 N/AforPkgType SN54HC166J ACTIVE CDIP J 16 1 TBD A42 N/AforPkgType SN74HC166D ACTIVE SOIC D 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DBR ACTIVE SSOP DB 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DBRE4 ACTIVE SSOP DB 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DBRG4 ACTIVE SSOP DB 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DE4 ACTIVE SOIC D 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DG4 ACTIVE SOIC D 16 40 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DR ACTIVE SOIC D 16 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DRE4 ACTIVE SOIC D 16 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DRG4 ACTIVE SOIC D 16 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DT ACTIVE SOIC D 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DTE4 ACTIVE SOIC D 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166DTG4 ACTIVE SOIC D 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166N ACTIVE PDIP N 16 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) SN74HC166NE4 ACTIVE PDIP N 16 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) SN74HC166NSR ACTIVE SO NS 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166NSRE4 ACTIVE SO NS 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166NSRG4 ACTIVE SO NS 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PW ACTIVE TSSOP PW 16 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWE4 ACTIVE TSSOP PW 16 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWG4 ACTIVE TSSOP PW 16 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWR ACTIVE TSSOP PW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWRE4 ACTIVE TSSOP PW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWRG4 ACTIVE TSSOP PW 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty noSb/Br) SN74HC166PWT ACTIVE TSSOP PW 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWTE4 ACTIVE TSSOP PW 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74HC166PWTG4 ACTIVE TSSOP PW 16 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SNJ54HC166FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N/AforPkgType SNJ54HC166J ACTIVE CDIP J 16 1 TBD A42 N/AforPkgType (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) SN74HC166DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC166DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC166NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC166PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC166DBR SSOP DB 16 2000 346.0 346.0 33.0 SN74HC166DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC166NSR SO NS 16 2000 346.0 346.0 33.0 SN74HC166PWR TSSOP PW 16 2000 346.0 346.0 29.0 PackMaterials-Page2

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN NO. OF A B 18 17 16 15 14 13 12 TERMINALS MIN MAX MIN MAX ** 0.342 0.358 0.307 0.358 19 11 20 (8,69) (9,09) (7,80) (9,09) 20 10 0.442 0.458 0.406 0.458 28 (11,23) (11,63) (10,31) (11,63) 21 9 B SQ 0.640 0.660 0.495 0.560 44 22 8 (16,26) (16,76) (12,58) (14,22) A SQ 23 7 0.739 0.761 0.495 0.560 52 (18,78) (19,32) (12,58) (14,22) 24 6 0.938 0.962 0.850 0.858 68 (23,83) (24,43) (21,6) (21,8) 25 5 1.141 1.165 1.047 1.063 84 (28,99) (29,59) (26,6) (27,0) 26 27 28 1 2 3 4 0.020 (0,51) 0.080 (2,03) 0.010 (0,25) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.045 (1,14) 0.022 (0,54) 0.035 (0,89) 0.050 (1,27) 4040140/D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,65 0,10 M 0,19 14 8 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 1 7 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 8 14 16 20 24 28 DIM A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9050101Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9050101Q2A SNJ54HC 166FK 5962-9050101QEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9050101QE A SNJ54HC166J 5962-9050101VEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9050101VE A SNV54HC166J SN54HC166J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HC166J SN74HC166D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166DRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC166N & no Sb/Br) SN74HC166NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SN74HC166PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC166 & no Sb/Br) SNJ54HC166FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 9050101Q2A SNJ54HC 166FK SNJ54HC166J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9050101QE A SNJ54HC166J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF SN54HC166, SN54HC166-SP, SN74HC166 : •Catalog: SN74HC166, SN54HC166 •Military: SN54HC166 •Space: SN54HC166-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC166DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC166DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC166DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC166PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC166PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC166PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC166DR SOIC D 16 2500 364.0 364.0 27.0 SN74HC166DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC166DRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74HC166PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HC166PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC166PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated