(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 (cid:1) Wide Operating Voltage Range of 2 V to 6 V (cid:1) Low Input Current of 1 µA Max (cid:1) (cid:1) Outputs Can Drive Up To 10 LSTTL Loads Internal Look-Ahead for Fast Counting (cid:1) Low Power Consumption, 80-µA Max I (cid:1) Carry Output for n-Bit Cascading CC (cid:1) (cid:1) Typical tpd = 14 ns Synchronous Counting (cid:1) ±4-mA Output Drive at 5 V (cid:1) Synchronously Programmable SN54HC161...J OR W PACKAGE SN54HC161...FK PACKAGE SN74HC161...D, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) KR CO LL C CC CC N V R CLR 1 16 VCC CLK 2 15 RCO 3 2 1 2019 A 3 14 QA A 4 18 QA B 4 13 Q B 5 17 QB B NC 6 16 NC C 5 12 Q C D 6 11 Q C 7 15 QC D D 8 14 Q ENP 7 10 ENT D 9 10 11 12 13 GND 8 9 LOAD P D C DT N N N AN E G OE L NC − No internal connection description/ordering information These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC161N SN74HC161N Tube of 40 SN74HC161D SSOOIICC −− DD Reel of 2500 SN74HC161DR HHCC116611 Reel of 250 SN74HC161DT −−4400°°CC ttoo 8855°°CC SOP − NS Reel of 2000 SN74HC161NSR HC161 Tube of 90 SN74HC161PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC161PWR HHCC116611 Reel of 250 SN74HC161PWT CDIP − J Tube of 25 SNJ54HC161J SNJ54HC161J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC161W SNJ54HC161W LCCC − FK Tube of 55 SNJ54HC161FK SNJ54HC161FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:21)(cid:16)(cid:17)(cid:22)(cid:18)(cid:6)(cid:14)(cid:13)(cid:17)(cid:2) (cid:22)(cid:19)(cid:14)(cid:19) (cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) (cid:23)(cid:31) !"(cid:27)(cid:27)#(cid:24)(cid:30) (cid:29)(cid:31) (cid:26)(cid:25) $"%&(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) ’(cid:29)(cid:30)#( Copyright  2003, Texas Instruments Incorporated (cid:21)(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28) (cid:30)(cid:26) (cid:31)$#!(cid:23)(cid:25)(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24)(cid:31) $#(cid:27) (cid:30))# (cid:30)#(cid:27)(cid:28)(cid:31) (cid:26)(cid:25) (cid:14)#*(cid:29)(cid:31) (cid:13)(cid:24)(cid:31)(cid:30)(cid:27)"(cid:28)#(cid:24)(cid:30)(cid:31) (cid:17)(cid:24) $(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:28)$&(cid:23)(cid:29)(cid:24)(cid:30) (cid:30)(cid:26) .(cid:13)/(cid:11)(cid:21)(cid:16)0(cid:11)12(cid:3)1(cid:3)(cid:9) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31) (cid:29)(cid:27)# (cid:30)#(cid:31)(cid:30)#’ (cid:31)(cid:30)(cid:29)(cid:24)’(cid:29)(cid:27)’ +(cid:29)(cid:27)(cid:27)(cid:29)(cid:24)(cid:30),( (cid:21)(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# "(cid:24)&#(cid:31)(cid:31) (cid:26)(cid:30))#(cid:27)+(cid:23)(cid:31)# (cid:24)(cid:26)(cid:30)#’( (cid:17)(cid:24) (cid:29)&& (cid:26)(cid:30))#(cid:27) $(cid:27)(cid:26)’"!(cid:30)(cid:31)(cid:9) $(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 description/ordering information (continued) These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse A can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 9 LOAD 10 ENT 15 RCO LD† 7 ENP CK† 2 CLK CK LD 1 CLR R M1 G2 1, 2T/1C3 14 G4 QA 3 A 3D 4R M1 G2 1, 2T/1C3 13 G4 QB 4 B 3D 4R M1 G2 1, 2T/1C3 12 G4 QC 5 C 3D 4R M1 G2 1, 2T/1C3 11 G4 QD 6 D 3D 4R †For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 Q (Output) G4 D (Inverted Data) 3D R (Inverted Reset) 4R logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG TG Q LD† TG CK† D CK† TG TG CK† CK† R †The origins of LD and CK are shown in the logic diagram of the overall device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Data Outputs QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC161 SN74HC161 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv‡‡ IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC161 SN74HC161 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC161 SN74HC161 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 6 4.2 5 ffcclloocckk CClloocckk ffrreeqquueennccyy 4.5 V 31 21 25 MMHHzz 6 V 36 25 29 2 V 80 120 100 CCLLKK hhiigghh oorr llooww 4.5 V 16 24 20 6 V 14 20 17 ttww PPuullssee dduurraattiioonn nnss 2 V 80 120 100 CCLLRR llooww 4.5 V 16 24 20 6 V 14 20 17 2 V 150 225 190 AA,, BB,, CC,, oorr DD 4.5 V 30 45 38 6 V 26 38 32 2 V 135 205 170 LLOOAADD llooww 4.5 V 27 41 34 6 V 23 35 29 ttssuu SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss 2 V 170 255 215 EENNPP,, EENNTT 4.5 V 34 51 43 6 V 29 43 37 2 V 125 190 155 CCLLRR iinnaaccttiivvee 4.5 V 25 38 31 6 V 21 32 26 2 V 0 0 0 tthh HHoolldd ttiimmee,, aallll ssyynncchhrroonnoouuss iinnppuuttss aafftteerr CCLLKK↑ 4.5 V 0 0 0 nnss 6 V 0 0 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC161 SN74HC161 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 6 14 4.2 5 ffmmaaxx 4.5 V 31 40 21 25 MMHHzz 6 V 36 44 25 29 2 V 83 215 325 270 RRCCOO 4.5 V 24 43 65 54 6 V 20 37 55 46 CCLLKK 2 V 80 205 310 255 ttppdd AAnnyy QQ 4.5 V 25 41 62 51 nnss 6 V 21 35 53 43 2 V 62 195 295 245 EENNTT RRCCOO 4.5 V 17 39 59 49 6 V 14 33 50 42 2 V 105 210 315 265 AAnnyy QQ 4.5 V 21 42 63 53 6 V 18 36 54 45 ttPPHHLL CCLLRR nnss 2 V 110 220 330 275 RRCCOO 4.5 V 22 44 66 55 6 V 19 37 56 47 2 V 38 75 110 95 tttt AAnnyy 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 60 pF 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC High-Level 50% 50% Pulse From Output Test 0 V Under Test Point tw CL = 50 pF Low-Level VCC (see Note A) Pulse 50% 50% 0 V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0 V tPLH tPHL ReferIennpcuet 50% VCC InO-Puhtapsuet 105%0% 90% 90% 501%0% VOH 0 V VOL tsu th tr tf tPHL tPLH Data VCC VOH Input 50% 90% 90% 50% Out-of-Phase 90% 50% 50% 90% 10% 10% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The ’HC161 devices count in binary. Virtually any count mode (modulo-N, N -to-N , N -to-maximum) 1 2 1 can be used with this fast look-ahead circuit. The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and 4.5-V V ). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every CC succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in addition to the bipolar equivalents (LS, ALS, AS). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION LSB Clear (L) CLR CT=0CTR LOAD M1 RCO Count (H)/ ENT 3CT=MAX G3 Disable (L) ENP G4 CLK C5/2,3,4+ Load (L) A 1,5D [1] QA Count (H)/ B [2] QB Disable (L) C [3] QC Clock D [4] QD CTR CLR CT=0 LOAD M1 RCO ENT 3CT=MAX G3 ENP G4 CLK C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CLR CT=0 LOAD M1 RCO ENT 3CT=MAX G3 ENP G4 CLK C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CLR CT=0 LOAD M1 RCO ENT 3CT=MAX G3 ENP G4 CLK C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD To More−Significant Stages Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION The glitch on RCO is caused because the propagation delay of the rising edge of Q of the second stage is A shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q , Q , Q , and Q A B C D (ENT × Q × Q × Q × Q ). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in A B C D which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to other stages. Q , Q , and Q of the first and second stage are at logic one, and Q of both stages are at logic B C D A zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q and RCO of the A first stage go high. On the rising edge of the third clock pulse, Q and RCO of the first stage return to a low level, A and Q of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears A because of the race condition inside the chip. 1 2 3 4 5 CLK ENT1 QB1, QC1, QD1 QA1 RCO1, ENT2 QB2, QC2, QD2 QA2 RCO2 Glitch (7−12 ns) Figure 3 The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t ). In other words, g f =1/(t CLK-to-RCO+t ). For example, at 25°C at 4.5-V V , the clock-to-RCO propagation delay is max pd g CC 43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the cascaded counters can use is 18 MHz. The following tables contain the f , t , and f specifications for clock w max applications that use more than two ’HC161 devices cascaded together. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7) (cid:4)(cid:11)(cid:12)(cid:13)(cid:14) (cid:1)(cid:15)(cid:2)(cid:6)(cid:5)(cid:16)(cid:17)(cid:2)(cid:17)(cid:18)(cid:1) (cid:12)(cid:13)(cid:2)(cid:19)(cid:16)(cid:15) (cid:6)(cid:17)(cid:18)(cid:2)(cid:14)(cid:20)(cid:16)(cid:1) SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC161 SN74HC161 VVCCCC UUNNIITT MIN MAX MIN MAX MIN MAX 2 V 3.6 2.5 2.9 ffcclloocckk CClloocckk ffrreeqquueennccyy 4.5 V 18 12 14 MMHHzz 6 V 21 14 17 2 V 140 200 170 ttww PPuullssee dduurraattiioonn,, CCLLKK hhiigghh oorr llooww 4.5 V 28 40 36 nnss 6 V 24 36 30 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Note 4) FFRROOMM TTOO TA = 25°C SN54HC161 SN74HC161 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN MAX MIN MAX MIN MAX UUNNIITT 2 V 3.6 2.5 2.9 ffmmaaxx 4.5 V 18 12 14 MMHHzz 6 V 21 14 17 NOTE 4: These limits apply only to applications that use more than two ’HC161 devices cascaded together. If the ’HC161 devices are used as a single unit, or only two cascaded together, then the maximum clock frequency that the device can use is not limited because of the glitch. In these situations, the device can be operated at the maximum specifications. A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any application that uses RCO to drive any input except an ENT of another cascaded ’HC161 device must take this into consideration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8407501VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8407501VE A SNV54HC161J 84075012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84075012A SNJ54HC 161FK 8407501EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407501EA SNJ54HC161J 8407501FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407501FA SNJ54HC161W JM38510/66302BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 66302BEA M38510/66302BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 66302BEA SN54HC161J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC161J SN74HC161D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161DG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161DRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161DT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC161N & no Sb/Br) SN74HC161NE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC161N & no Sb/Br) SN74HC161NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HC161PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SN74HC161PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC161 & no Sb/Br) SNJ54HC161FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84075012A SNJ54HC 161FK SNJ54HC161J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407501EA SNJ54HC161J SNJ54HC161W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407501FA SNJ54HC161W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC161, SN54HC161-SP, SN74HC161 : •Catalog: SN74HC161, SN54HC161 •Military: SN54HC161 •Space: SN54HC161-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC161DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC161NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC161PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC161PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC161DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC161NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC161PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC161PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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