Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 SNx4HC132 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 1 Features 3 Description • WideOperatingVoltageRangeof2Vto6V The SNx4HC132 device functions as a NAND gate, 1 but because of the Schmitt action, it has different • OutputsCanDriveupto10LSTTLLoads input threshold levels for positive and negative going • LowPowerConsumption,20-µAMaximumICC signals. The SNx4HC132 devices perform the • Typicalt =14ns Boolean function pd Y= A•BorY= A+Binpositivelogic. • ±4-mAOutputDriveat5V • LowInputCurrentof1 µAMaximum These circuits are temperature compensated and can be triggered from the slowest of input ramps and still • OperationfromVerySlowInputTransitions givecleanjitter-freeoutputsignals. • Temperature-CompensatedThresholdLevels • HighNoiseImmunity DeviceInformation(1) • SamePinoutsasSN74HC00 PACKAGE PARTNUMBER BODYSIZE(NOM) (PINS) 2 Applications SN54HC132J CDIP(14) 19.56mm×6.67mm SN74HC132D SOIC(14) 4.90mm×3.91mm • ElectronicPoints-of-Sale SN74HC132N PDIP(14) 19.30mm×6.35mm • TelecomInfrastructure SN54HC132FK LCCC(20) 8.89mm×8.89mm • NetworkSwitches SN54HC132W CFP(14) 9.21mm×5.97mm • TestsandMeasurements SN74HC132PW TSSOP(14) 5.00mm×4.40mm SN74HC132NS SO(14) 10.30mm×5.30mm SN74HC132DB SSOP(14) 6.20mm×5.30mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. LogicDiagram(PositiveLogic) A Y B 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. On products compliant to MIL-PRF-38535, all parameters are testedunlessotherwisenoted.Onallotherproducts,production processingdoesnotnecessarilyincludetestingofallparameters.

SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription...................................................8 2 Applications........................................................... 1 8.4 DeviceFunctionalModes..........................................8 3 Description............................................................. 1 9 ApplicationandImplementation.......................... 9 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation..............................................9 9.2 TypicalApplication ...................................................9 5 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 10 6 Specifications......................................................... 4 11 Layout................................................................... 10 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 11.1 LayoutGuidelines.................................................10 6.3 RecommendedOperatingConditions.......................4 11.2 LayoutExample....................................................10 6.4 ThermalInformation .................................................4 12 DeviceandDocumentationSupport................. 11 6.5 ElectricalCharacteristics...........................................5 12.1 DocumentationSupport........................................11 6.6 SwitchingCharacteristics..........................................6 12.2 RelatedLinks........................................................11 6.7 OperatingCharacteristics..........................................6 12.3 ReceivingNotificationofDocumentationUpdates11 6.8 TypicalCharacteristics..............................................6 12.4 CommunityResources..........................................11 7 ParameterMeasurementInformation..................7 12.5 Trademarks...........................................................11 12.6 ElectrostaticDischargeCaution............................11 8 DetailedDescription.............................................. 8 12.7 Glossary................................................................11 8.1 Overview...................................................................8 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.........................................8 Information........................................................... 11 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(November2004)toRevisionG Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • RemovedOrderingInformationtable,seePOAattheendofthedatasheet........................................................................ 1 2 SubmitDocumentationFeedback Copyright©1982–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 www.ti.com SCLS034G–DECEMBER1982–REVISEDJUNE2016 5 Pin Configuration and Functions D,DB,N,NS,J,W,orPWPackage FKPackage 14-PinSOIC,SSOP,PDIP,SO,orTSSOP 20-PinLCCC TopView TopView C 1A 1 14 VCC 1B 1A NC VC4B 1B 2 13 4B 1Y 3 12 4A 3 2 1 0 9 2 1 2A 4 11 4Y 1Y 4 18 4A 2B 5 10 3B NC 5 17 NC 2Y 6 9 3A 2A 6 16 4Y GND 7 8 3Y NC 7 15 NC 2B 8 14 3B Not to scale 0 1 2 3 9 1 1 1 1 Not to scale Y D C Y A 2 N N 3 3 G PinFunctions(1) PIN SOIC,SSOP, I/O DESCRIPTION NAME PDIP,SO, LCCC TSSOP 1A 1 2 I 1AInput 1B 2 3 I 1BInput 1Y 3 4 O 1YOutput 2A 4 6 I 2AInput 2B 5 8 I 2BInput 2Y 6 9 O 2YOutput 3A 9 13 I 3AInput 3B 10 14 I 3BInput 3Y 8 12 O 3YOutput 4A 12 18 I 4AInput 4B 13 19 I 4BInput 4Y 11 16 O 4YOutput GND 7 10 — GroundPin 1,5,7,11,15, NC — — NoConnection 17 V 14 20 — PowerPin CC (1) NC–noconnection Copyright©1982–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC I Inputclampcurrent(2) V <0orV >V ±20 mA IK I I CC I Outputclampcurrent(2) V <0orV >V ±20 mA OK O O CC I Continuousoutputcurrent V =0toV ±25 mA O O CC ContinuouscurrentthroughV orGND ±50 mA CC T Junctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions See (1) MIN NOM MAX UNIT V Supplyvoltage 2 5 6 V CC V Inputvoltage 0 V V I CC V Outputvoltage 0 V V O CC SN54HC132 –55 125 T Operatingfree-airtemperature °C A SN74HC132 –40 85 (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs. 6.4 Thermal Information SN74HC132 THERMALMETRIC(1) D DB N NS PW UNIT (SOIC) (SSOP) (PDIP) (SO) (TSSOP) 14PINS 14PINS 14PINS 14PINS 14PINS RθJA Junction-to-ambientthermalresistance(2) 84.3 99.1 50.9 84.3 113.3 °C/W RθJC(top) Junction-to-case(top)thermalresistance 44.8 51.3 38.2 42.2 42.8 °C/W RθJB Junction-to-boardthermalresistance 38.5 46.3 30.8 43.0 54.8 °C/W ψJT Junction-to-topcharacterizationparameter 13.9 17.7 23.1 13.5 4.0 °C/W ψJB Junction-to-boardcharacterizationparameter 38.2 45.8 30.7 42.7 54.3 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheapplicationreport,SemiconductorandICPackageThermal Metrics. (2) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. 4 SubmitDocumentationFeedback Copyright©1982–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 www.ti.com SCLS034G–DECEMBER1982–REVISEDJUNE2016 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 2V 0.7 1.2 1.5 V 4.5V 1.55 2.5 3.15 V T+ 6V 2.1 3.3 4.2 2V 0.3 0.6 1 V 4.5V 0.9 1.6 2.45 V T− 6V 1.2 2 3.2 2V 0.2 0.6 1.2 V –V 4.5V 0.4 0.9 2.1 V T+ T− 6V 0.5 1.3 2.5 2V 1.9 1.998 I =–20µA 4.5V 4.4 4.499 OH 6V 5.9 5.999 T =25°C 3.98 4.3 A V V =V orV I =–4mA SN54HC132 4.5V 3.7 V OH I IH IL OH SN74HC132 3.84 T =25°C 5.48 5.8 A I =–5.2mA SN54HC132 6V 5.2 OH SN74HC132 5.34 2V 0.002 0.1 I =20µA 4.5V 0.001 0.1 OL 6V 0.001 0.1 T =25°C 0.17 0.26 A V V =V orV I =4mA SN54HC132 4.5V 0.4 V OL I IH IL OL SN74HC132 0.33 T =25°C 0.15 0.26 A I =5.2mA SN54HC132 6V 0.4 OL SN74HC132 0.33 T =25°C ±0.1 ±100 A II VI=VCCor0 SN54HC132, 6V nA ±1000 SN74HC132 T =25°C 2 A I V =V or0,I =0 SN54HC132 6V 40 µA CC I CC O SN74HC132 20 C 2Vto6V 3 10 pF i Copyright©1982–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 www.ti.com 6.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =50pF(unlessotherwisenoted)(seeFigure3) L FROM TO PARAMETER V T MIN TYP MAX UNIT (INPUT) (OUTPUT) CC A T =25°C 60 120 A 2V SN54HC132 186 SN74HC132 156 T =25°C 18 25 A t AorB Y 4.5V SN54HC132 37 ns pd SN74HC132 31 T =25°C 14 21 A 6V SN54HC132 32 SN74HC132 27 T =25°C 28 75 A 2V SN54HC132 110 SN74HC132 95 T =25°C 8 15 A t Any 4.5V SN54HC132 22 ns t SN74HC132 19 T =25°C 6 13 A 6V SN54HC132 19 SN74HC132 16 6.7 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitancepergate Noload 20 pF pd 6.8 Typical Characteristics 60 30 50 25 40 20 t (ns) PD30 t (ns) t15 20 10 10 5 CL=50pF CL=50pF 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V (V) V (V) CC C002 CC C001 Figure1.PropagationDelayvsV Figure2.TransitionTimevsV CC CC 6 SubmitDocumentationFeedback Copyright©1982–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 www.ti.com SCLS034G–DECEMBER1982–REVISEDJUNE2016 7 Parameter Measurement Information From Output Test VCC UnderTest Point Input 50% 50% 0 V CL= 50 pF (see NoteA) tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% LOAD CIRCUIT 10% 10% VOL tr tf 90% 90% VCC tPHL tPLH VOH Input 105%0% 501%0% Out-of-Phase 90% 50% 50% 90% 0 V Output 10% 10% VOL tr tf tf tr VOLTAGEWAVEFORM VOLTAGEWAVEFORMS INPUTRISEANDFALLTIMES PROPAGATION DELAYAND OUTPUT TRANSITION TIMES NOTES: A. CLincludes probe and test-fixture capacitance. B. Phaserelationshipsbetweenwaveformswerechosenarbitrarily.Allinputpulsesaresuppliedbygeneratorshavingthefollowing characteristics:PRR≤1 MHz, ZO= 50Ω, tr= 6 ns, tf= 6 ns. C. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. D. tPLHand tPHLare the same as tpd. Figure3. LoadCircuitandVoltageWaveforms Copyright©1982–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 www.ti.com 8 Detailed Description 8.1 Overview The SNx4HC132 is a quadruple 2-input positive-NAND gate with low drive that produces slow rise and fall times. Thisreducesringingontheoutputsignal. Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels forpositive-andnegative-goingsignals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean,jitter-freeoutputsignals. 8.2 Functional Block Diagram A Y B Figure4. LogicDiagram(PositiveLogic) 8.3 Feature Description The SNx4HC132 has a wide operating range of 2 V to 6 V. The SNx4HC132 also has a low power consumption wherethemaximumICCis20µA. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSNx4HC132. Table1.FunctionTable(EachGate) INPUTS OUTPUT A B Y H H L L X H X L H 8 SubmitDocumentationFeedback Copyright©1982–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 www.ti.com SCLS034G–DECEMBER1982–REVISEDJUNE2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74HC132 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates minimize overshoot and undershoot on the outputs.TheinputscanacceptvoltagestoV .Thecurrentconsumptionofthedeviceislowwithmaximum CC 20-µAI . CC 9.2 Typical Application 3.3- or 5-VAccessory 5-V Regulated 0.1µF Figure5. TypicalApplicationDiagram 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so considerroutingandloadconditionstopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions: – Forrisetimeandfalltimespecifications,see Δt/ΔVintheRecommendedOperatingConditions table. – Forspecifiedhighandlowlevels,seeV andV intheRecommendedOperatingConditions table. IH IL 2. RecommendOutputConditions: – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart. – OutputsmustnotbepulledaboveV . CC Copyright©1982–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 SCLS034G–DECEMBER1982–REVISEDJUNE2016 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve AC132 HC132 AHC132 Figure6. SwitchingCharacteristicsComparison 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply-voltage rating located in the RecommendedOperatingConditionstable. EachV pinmusthaveagoodbypasscapacitortopreventpowerdisturbance.Fordeviceswithasinglesupply, CC 0.1 µF is recommended. If there are multiple V pins then a 0.01 µF or a 0.022 µF is recommended for each CC powerpin.Itisacceptabletoparallelmultiplebypasscapstorejectdifferentfrequenciesofnoise.A0.1 µFanda 1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possibleforbestresults. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or V , whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a CC transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted. ThisdoesnotdisabletheinputsectionoftheI/Ossotheyalsocannotfloatwhendisabled. 11.2 Layout Example V cc Input Unused Input Output Unused Input Output Input Figure7. LayoutDiagram 10 SubmitDocumentationFeedback Copyright©1982–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN54HC132SN74HC132

SN54HC132 SN74HC132 www.ti.com SCLS034G–DECEMBER1982–REVISEDJUNE2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54HC132 Clickhere Clickhere Clickhere Clickhere Clickhere SN74HC132 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1982–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54HC132SN74HC132

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-89845022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 89845022A SNJ54HC 132FK 5962-8984502CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502CA SNJ54HC132J 5962-8984502DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502DA SNJ54HC132W 5962-8984502VCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502VC A SNV54HC132J 5962-8984502VDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502VD A SNV54HC132W SN54HC132J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HC132J SN74HC132D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DE4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132DTE4 ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HC132N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC132N & no Sb/Br) SN74HC132NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC132N & no Sb/Br) SN74HC132NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132NSRG4 ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SN74HC132PWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC132 & no Sb/Br) SNJ54HC132FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 89845022A SNJ54HC 132FK SNJ54HC132J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502CA SNJ54HC132J SNJ54HC132W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8984502DA SNJ54HC132W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC132, SN54HC132-SP, SN74HC132 : •Catalog: SN74HC132, SN54HC132 •Automotive: SN74HC132-Q1, SN74HC132-Q1 •Military: SN54HC132 •Space: SN54HC132-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC132DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC132PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC132PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC132DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC132DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC132DT SOIC D 14 250 210.0 185.0 35.0 SN74HC132PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC132PWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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