(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:13)(cid:17)(cid:18)(cid:19) (cid:20)(cid:13)(cid:1) (cid:20)(cid:13)(cid:21)(cid:21)(cid:19)(cid:16) (cid:22)(cid:14)(cid:23)(cid:19)(cid:1) (cid:24)(cid:25)(cid:23)(cid:5) (cid:26)(cid:27)(cid:1)(cid:23)(cid:14)(cid:23)(cid:19) (cid:28)(cid:13)(cid:23)(cid:17)(cid:13)(cid:23)(cid:1) SCLS103E − MARCH 1984 − REVISED JULY 2003 (cid:1) (cid:1) Wide Operating Voltage Range of 2 V to 6 V Typical tpd = 11 ns (cid:1) High-Current 3-State Outputs Interface (cid:1) ±6-mA Output Drive at 5 V Directly With System Bus or Can Drive Up (cid:1) Low Input Current of 1 µA Max To 15 LSTTL Loads (cid:1) Low Power Consumption, 80-µA Max I CC SN54HC126...J OR W PACKAGE SN54HC126...FK PACKAGE SN74HC126...D, DB, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) E CE A O C CO 1 1 N V 4 1OE 1 14 VCC 1A 2 13 4OE 1Y 43 2 1 20 1918 4A 1Y 3 12 4A NC 5 17 NC 2OE 4 11 4Y 2OE 6 16 4Y 2A 5 10 3OE NC 7 15 NC 2Y 6 9 3A 2A 8 14 3OE GND 7 8 3Y 9 10 1112 13 YD CY A 2N N3 3 G NC − No internal connection description/ordering information These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC126N SN74HC126N Tube of 50 SN74HC126D SSOOIICC −− DD Reel of 2500 SN74HC126DR HHCC112266 Reel of 250 SN74HC126DT −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HC126NSR HC126 SSOP − DB Reel of 2000 SN74HC126DBR HC126 Tube of 90 SN74HC126PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HC126PWR HHCC112266 Reel of 250 SN74HC126PWT CDIP − J Tube of 25 SNJ54HC126J SNJ54HC126J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC126W SNJ54HC126W LCCC − FK Tube of 55 SNJ54HC126FK SNJ54HC126FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:17)(cid:16)(cid:28)(cid:15)(cid:13)(cid:6)(cid:23)(cid:25)(cid:28)(cid:2) (cid:15)(cid:14)(cid:23)(cid:14) (cid:29)(cid:30)(cid:31)!"#$%(cid:29)!(cid:30) (cid:29)& ’("")(cid:30)% $& !(cid:31) *(+,(cid:29)’$%(cid:29)!(cid:30) -$%). Copyright  2003, Texas Instruments Incorporated (cid:17)"!-(’%& ’!(cid:30)(cid:31)!"# %! &*)’(cid:29)(cid:31)(cid:29)’$%(cid:29)!(cid:30)& *)" %/) %)"#& !(cid:31) (cid:23))0$& (cid:25)(cid:30)&%"(#)(cid:30)%& (cid:28)(cid:30) *"!-(’%& ’!#*,(cid:29)$(cid:30)% %! 4(cid:25)(cid:18)(cid:27)(cid:17)(cid:16)(cid:21)(cid:27)(cid:26)5(cid:3)(cid:26)(cid:3)(cid:10) $,, *$"$#)%)"& $") %)&%)- &%$(cid:30)-$"- 1$""$(cid:30)%2. (cid:17)"!-(’%(cid:29)!(cid:30) *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) ((cid:30),)&& !%/)"1(cid:29)&) (cid:30)!%)-. (cid:28)(cid:30) $,, !%/)" *"!-(’%&(cid:10) *"!-(’%(cid:29)!(cid:30) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:13)(cid:17)(cid:18)(cid:19) (cid:20)(cid:13)(cid:1) (cid:20)(cid:13)(cid:21)(cid:21)(cid:19)(cid:16) (cid:22)(cid:14)(cid:23)(cid:19)(cid:1) (cid:24)(cid:25)(cid:23)(cid:5) (cid:26)(cid:27)(cid:1)(cid:23)(cid:14)(cid:23)(cid:19) (cid:28)(cid:13)(cid:23)(cid:17)(cid:13)(cid:23)(cid:1) SCLS103E − MARCH 1984 − REVISED JULY 2003 FUNCTION TABLE (each buffer) INPUTS OOUUTTPPUUTT OE A Y H H H H L L L X Z logic diagram (positive logic) 1 10 1OE 3OE 2 3 9 8 1A 1Y 3A 3Y 4 13 2OE 4OE 5 6 12 11 2A 2Y 4A 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:13)(cid:17)(cid:18)(cid:19) (cid:20)(cid:13)(cid:1) (cid:20)(cid:13)(cid:21)(cid:21)(cid:19)(cid:16) (cid:22)(cid:14)(cid:23)(cid:19)(cid:1) (cid:24)(cid:25)(cid:23)(cid:5) (cid:26)(cid:27)(cid:1)(cid:23)(cid:14)(cid:23)(cid:19) (cid:28)(cid:13)(cid:23)(cid:17)(cid:13)(cid:23)(cid:1) SCLS103E − MARCH 1984 − REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HC126 SN74HC126 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC126 SN74HC126 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IIOOHH == −−2200 µµAA 4.5 V 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 6 V 5.9 5.999 5.9 5.9 VV IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 2 V to 6 V 3 10 10 10 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:13)(cid:17)(cid:18)(cid:19) (cid:20)(cid:13)(cid:1) (cid:20)(cid:13)(cid:21)(cid:21)(cid:19)(cid:16) (cid:22)(cid:14)(cid:23)(cid:19)(cid:1) (cid:24)(cid:25)(cid:23)(cid:5) (cid:26)(cid:27)(cid:1)(cid:23)(cid:14)(cid:23)(cid:19) (cid:28)(cid:13)(cid:23)(cid:17)(cid:13)(cid:23)(cid:1) SCLS103E − MARCH 1984 − REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC126 SN74HC126 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 47 120 180 150 ttppdd AA YY 4.5 V 14 24 36 30 nnss 6 V 11 20 31 26 2 V 57 120 180 150 tteenn OOEE YY 4.5 V 16 24 36 30 nnss 6 V 12 20 31 26 2 V 35 120 180 150 ttddiiss OOEE YY 4.5 V 17 24 36 30 nnss 6 V 15 20 31 26 2 V 28 60 90 75 tttt AAnnyy 4.5 V 8 12 18 15 nnss 6 V 6 10 15 13 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC126 SN74HC126 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 67 150 225 188 ttppdd AA YY 4.5 V 19 30 45 38 nnss 6 V 15 25 39 33 2 V 100 135 202 169 tteenn OOEE YY 4.5 V 20 27 40 36 nnss 6 V 17 23 36 30 2 V 45 210 315 265 tttt AAnnyy 4.5 V 17 42 63 53 nnss 6 V 13 36 53 45 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate No load 45 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:13)(cid:17)(cid:18)(cid:19) (cid:20)(cid:13)(cid:1) (cid:20)(cid:13)(cid:21)(cid:21)(cid:19)(cid:16) (cid:22)(cid:14)(cid:23)(cid:19)(cid:1) (cid:24)(cid:25)(cid:23)(cid:5) (cid:26)(cid:27)(cid:1)(cid:23)(cid:14)(cid:23)(cid:19) (cid:28)(cid:13)(cid:23)(cid:17)(cid:13)(cid:23)(cid:1) SCLS103E − MARCH 1984 − REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 Test S1 ten tPZH 1 kΩ 50o prF Open Closed From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL tdis 1 kΩ 50 pF (see Note A) S2 tPLZ Closed Open 50 pF tpd or tt −− or Open Open 150 pF LOAD CIRCUIT VCC Input 50% 50% 0 V tPLH tPHL In-Phase VOH 90% 90% Output 50% 50% 10% 10% VOL tr tf tPHL tPLH Output VCC VOH Control 50% 50% Out-of-Phase 90% 50% 50% 90% 0 V Output 10% 10% VOL tPZL tPLZ tf tr Output ≈VCC Waveform 1 50% VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES (See Note B) 10% VOL tPZH tPHZ VCC Output VOH 90% 90% 90% Input 50% 50% Waveform 2 50% 10% 10% 0 V (See Note B) ≈0 V tr tf VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-86848012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 86848012A SNJ54HC 126FK 5962-8684801CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8684801CA SNJ54HC126J SN54HC126J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54HC126J SN74HC126D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126DRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC126N & no Sb/Br) SN74HC126NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126PWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SN74HC126PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC126 & no Sb/Br) SNJ54HC126FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 86848012A SNJ54HC Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 126FK SNJ54HC126J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8684801CA SNJ54HC126J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC126, SN74HC126 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: SN74HC126 •Military: SN54HC126 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC126DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC126NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC126PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC126DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC126DT SOIC D 14 250 210.0 185.0 35.0 SN74HC126NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC126PWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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