(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:19)(cid:20)(cid:21)(cid:2)(cid:16)(cid:12)(cid:22) (cid:16)(cid:23)(cid:1)(cid:21)(cid:22)(cid:21)(cid:24)(cid:18)(cid:20)(cid:2)(cid:13)(cid:2)(cid:14) (cid:25)(cid:13)(cid:22)(cid:18)(cid:1) (cid:26)(cid:21)(cid:22)(cid:5) (cid:23)(cid:16)(cid:18)(cid:2)(cid:20)(cid:14)(cid:15)(cid:13)(cid:21)(cid:2) (cid:23)(cid:12)(cid:22)(cid:16)(cid:12)(cid:22)(cid:1) SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 (cid:1) (cid:1) Wide Operating Voltage Range of 2 V to 6 V Typical tpd = 8 ns (cid:1) Outputs Can Drive Up To 10 LSTTL Loads (cid:1) ±4-mA Output Drive at 5 V (cid:1) Low Power Consumption, 20-µA Max I (cid:1) Low Input Current of 1 µA Max CC SN54HC03...J OR W PACKAGE SN54HC03...FK PACKAGE SN74HC03...D, N, NS, OR PW PACKAGE (TOP VIEW) (TOP VIEW) C B A C CB 1 1 N V 4 1A 1 14 VCC 3 2 1 20 19 1B 2 13 4B 1Y 4 18 4A 1Y 3 12 4A NC 5 17 NC 2A 4 11 4Y 2A 6 16 4Y 2B 5 10 3B NC 7 15 NC 2Y 6 9 3A 2B 8 14 3B GND 7 8 3Y 9 10 1112 13 YD CY A 2N N3 3 G NC − No internal connection description/ordering information The ’HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 25 SN74HC03N SN74HC03N Tube of 50 SN74HC03D SSOOIICC −− DD Reel of 2500 SN74HC03DR HHCC0033 −−4400°CC ttoo 8855°CC Reel of 250 SN74HC03DT SOP − NS Reel of 2000 SN74HC03NSR HC03 Tube of 90 SN74HC03PW TTSSSSOOPP −− PPWW HHCC0033 Reel of 2000 SN74HC03PWR CDIP − J Tube of 25 SNJ54HC03J SNJ54HC03J −−5555°CC ttoo 112255°CC CFP − W Tube of 150 SNJ54HC03W SNJ54HC03W LCCC − FK Tube of 55 SNJ54HC03FK SNJ54HC03FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:16)(cid:15)(cid:23)(cid:14)(cid:12)(cid:6)(cid:22)(cid:21)(cid:23)(cid:2) (cid:14)(cid:13)(cid:22)(cid:13) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  2003, Texas Instruments Incorporated (cid:16)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:22)’."$ (cid:21)(cid:28)$#(cid:31)&!’(cid:28)#$ (cid:23)(cid:28) ((cid:31)(cid:30)+&%#$ %(cid:30)!(*(cid:27)"(cid:28)# #(cid:30) 2(cid:21)(cid:17)(cid:20)(cid:16)(cid:15)3(cid:20)(cid:8)4(cid:3)(cid:8)(cid:3)(cid:9) "** ("(cid:31)"!’#’(cid:31)$ "(cid:31)’ #’$#’+ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:16)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ &(cid:28)*’$$ (cid:30)#-’(cid:31)/(cid:27)$’ (cid:28)(cid:30)#’+, (cid:23)(cid:28) "** (cid:30)#-’(cid:31) ((cid:31)(cid:30)+&%#$(cid:9) ((cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:19)(cid:20)(cid:21)(cid:2)(cid:16)(cid:12)(cid:22) (cid:16)(cid:23)(cid:1)(cid:21)(cid:22)(cid:21)(cid:24)(cid:18)(cid:20)(cid:2)(cid:13)(cid:2)(cid:14) (cid:25)(cid:13)(cid:22)(cid:18)(cid:1) (cid:26)(cid:21)(cid:22)(cid:5) (cid:23)(cid:16)(cid:18)(cid:2)(cid:20)(cid:14)(cid:15)(cid:13)(cid:21)(cid:2) (cid:23)(cid:12)(cid:22)(cid:16)(cid:12)(cid:22)(cid:1) SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H H L L X H X L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC03 SN74HC03 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 3.15 VV VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 1.35 VV VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆∆tt//∆∆vv IInnppuutt ttrraannssiittiioonn rriissee//ffaallll ttiimmee VCC = 4.5 V 500 500 nnss VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:19)(cid:20)(cid:21)(cid:2)(cid:16)(cid:12)(cid:22) (cid:16)(cid:23)(cid:1)(cid:21)(cid:22)(cid:21)(cid:24)(cid:18)(cid:20)(cid:2)(cid:13)(cid:2)(cid:14) (cid:25)(cid:13)(cid:22)(cid:18)(cid:1) (cid:26)(cid:21)(cid:22)(cid:5) (cid:23)(cid:16)(cid:18)(cid:2)(cid:20)(cid:14)(cid:15)(cid:13)(cid:21)(cid:2) (cid:23)(cid:12)(cid:22)(cid:16)(cid:12)(cid:22)(cid:1) SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC03 SN74HC03 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH VI = VIH or VIL, VO = VCC 6 V 0.01 0.5 10 5 µA 2 V 0.002 0.1 0.1 0.1 IIOOLL == 2200 µµAA 4.5 V 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 6 V 0.001 0.1 0.1 0.1 VV IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA Ci 2 V to 6 V 3 10 10 10 pF switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HC03 SN74HC03 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 2 V 60 105 155 131 ttPPLLHH AA oorr BB YY 4.5 V 13 25 36 31 nnss 6 V 10 23 31 27 2 V 50 100 150 125 ttPPHHLL AA oorr BB YY 4.5 V 10 20 30 25 nnss 6 V 8 17 25 21 2 V 38 75 110 95 ttff YY 4.5 V 8 15 22 19 nnss 6 V 6 13 19 16 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate No load 20 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:12)(cid:16)(cid:17)(cid:18) (cid:19)(cid:20)(cid:21)(cid:2)(cid:16)(cid:12)(cid:22) (cid:16)(cid:23)(cid:1)(cid:21)(cid:22)(cid:21)(cid:24)(cid:18)(cid:20)(cid:2)(cid:13)(cid:2)(cid:14) (cid:25)(cid:13)(cid:22)(cid:18)(cid:1) (cid:26)(cid:21)(cid:22)(cid:5) (cid:23)(cid:16)(cid:18)(cid:2)(cid:20)(cid:14)(cid:15)(cid:13)(cid:21)(cid:2) (cid:23)(cid:12)(cid:22)(cid:16)(cid:12)(cid:22)(cid:1) SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ From Output Test VCC Input 50% 50% Under Test Point 0 V CL = 50 pF (see Note A) tPLH tPHL In-Phase VOH 90% Output 50% LOAD CIRCUIT 10% 10%VOL tf VCC tPHL tPLH Input 105%0% 90% 90% 501%0% Out-of-Phase 90% 50% VOH 0 V Output 10% 10% tr tf tf VOL VOLTAGE WAVEFORM VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-87647012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87647012A SNJ54HC 03FK 5962-8764701CA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8764701CA SNJ54HC03J SN54HC03J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54HC03J SN74HC03D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03DT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC03N & no Sb/Br) SN74HC03NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74HC03N & no Sb/Br) SN74HC03NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SN74HC03PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HC03 & no Sb/Br) SNJ54HC03FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 87647012A SNJ54HC 03FK SNJ54HC03J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8764701CA SNJ54HC03J Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC03, SN74HC03 : •Catalog: SN74HC03 •Military: SN54HC03 NOTE: Qualified Version Definitions: Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HC03DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC03DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC03PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HC03DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC03DT SOIC D 14 250 210.0 185.0 35.0 SN74HC03PWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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