(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:12)(cid:19)(cid:20)(cid:17)(cid:17)(cid:15)(cid:19)(cid:15)(cid:16)(cid:9)(cid:16)(cid:18)(cid:12)(cid:21)(cid:22)(cid:15)(cid:9)(cid:5)(cid:14)(cid:20)(cid:22)(cid:18)(cid:5)(cid:14)(cid:10)(cid:22)(cid:1) (cid:23)(cid:20)(cid:12)(cid:24)(cid:9)(cid:6)(cid:18)(cid:1)(cid:12)(cid:13)(cid:12)(cid:15)(cid:9)(cid:10)(cid:25)(cid:12)(cid:22)(cid:25)(cid:12)(cid:1) SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993 • Eight D-Type Flip-Flops in a Single Package SN54F374...J PACKAGE • SN74F374... DB, DW, OR N PACKAGE 3-State Bus-Driving True Outputs (TOP VIEW) • Full Parallel Access for Loading • Buffered Control Inputs OE 1 20 VCC • Package Options Include Plastic 1Q 2 19 8Q Small-Outline (SOIC) and Shrink 1D 3 18 8D Small-Outline (SSOP) Packages, Ceramic 2D 4 17 7D Chip Carriers, and Plastic and Ceramic 2Q 5 16 7Q DIPs 3Q 6 15 6Q 3D 7 14 6D description 4D 8 13 5D 4Q 9 12 5Q These 8-bit flip-flops feature 3-state outputs GND 10 11 CLK designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer SN54F374...FK PACKAGE (TOP VIEW) registers, I/O ports, bidirectional bus drivers, and working registers. D Q E CCQ 1 1 OV 8 The eight flip-flops of the ′F374 are edge-triggered D-type flip-flops. On the positive transition of the 3 2 1 20 19 2D 4 18 8D clock (CLK) input, the Q outputs are set to the logic 2Q 5 17 7D levels that were set up at the data (D) inputs. 3Q 6 16 7Q A buffered output enable (OE) input can be used 3D 7 15 6Q to place the eight outputs in either a normal logic 4D 8 14 6D 9 10 11 12 13 state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither Q D KQ D load nor drive the bus lines significantly. The 4 GN CL5 5 high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54F374 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74F374 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT OE CLK D Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z (cid:22)(cid:19)(cid:10)(cid:16)(cid:25)(cid:11)(cid:12)(cid:20)(cid:10)(cid:2) (cid:16)(cid:13)(cid:12)(cid:13) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  1993, Texas Instruments Incorporated (cid:22)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:12)&-!# (cid:20)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:22)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2−1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:12)(cid:19)(cid:20)(cid:17)(cid:17)(cid:15)(cid:19)(cid:15)(cid:16)(cid:9)(cid:16)(cid:18)(cid:12)(cid:21)(cid:22)(cid:15)(cid:9)(cid:5)(cid:14)(cid:20)(cid:22)(cid:18)(cid:5)(cid:14)(cid:10)(cid:22)(cid:1) (cid:23)(cid:20)(cid:12)(cid:24)(cid:9)(cid:6)(cid:18)(cid:1)(cid:12)(cid:13)(cid:12)(cid:15)(cid:9)(cid:10)(cid:25)(cid:12)(cid:22)(cid:25)(cid:12)(cid:1) SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993 logic symbol† logic diagram (positive logic) 1 1 OE OE EN 11 11 CLK C1 CLK C1 2 3 2 3 1Q 1D 1D 1Q 1D 1D 4 5 2D 2Q 7 6 3D 3Q 8 9 4D 4Q 13 12 5D 5Q 14 15 To Seven Other Channels 6D 6Q 17 16 7D 7Q 18 19 8D 8Q †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V I Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V CC Current into any output in the low state:SN54F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SN74F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Operating free-air temperature range: SN54F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74F374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions SN54F374 SN74F374 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IIK Input clamp current −18 −18 mA IOH High-level output current −3 −3 mA IOL Low-level output current 20 24 mA TA Operating free-air temperature −55 125 0 70 °C 2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:12)(cid:19)(cid:20)(cid:17)(cid:17)(cid:15)(cid:19)(cid:15)(cid:16)(cid:9)(cid:16)(cid:18)(cid:12)(cid:21)(cid:22)(cid:15)(cid:9)(cid:5)(cid:14)(cid:20)(cid:22)(cid:18)(cid:5)(cid:14)(cid:10)(cid:22)(cid:1) (cid:23)(cid:20)(cid:12)(cid:24)(cid:9)(cid:6)(cid:18)(cid:1)(cid:12)(cid:13)(cid:12)(cid:15)(cid:9)(cid:10)(cid:25)(cid:12)(cid:22)(cid:25)(cid:12)(cid:1) SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54F374 SN74F374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V IOH = −1 mA 2.5 3.4 2.5 3.4 VVCCCC == 44..55 VV VOH IOH = −3 mA 2.4 3.3 2.4 3.3 V VCC = 4.75 V, IOH = −1 mA to −3 mA 2.7 IOL = 20 mA 0.3 0.5 VVOOLL VVCCCC == 44..55 VV VV IOL = 24 mA 0.35 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA IOZL VCC = 5.5 V, VO = 0.5 V −50 −50 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL VCC = 5.5 V, VI = 0.5 V −0.6 −0.6 mA IOS‡ VCC = 5.5 V, VO = 0 −60 −150 −60 −150 mA ICCZ VCC = 5.5 V, See Note 2 55 86 55 86 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICCZ is measured with OE at 4.5 V and all other inputs grounded. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SSNN5544FF337744 SSNN7744FF337744 UUNNIITT ′F374 MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 100 0 60 0 70 MHz CLK high 7 7 7 ttww PPuullssee dduurraattiioonn nnss CLK low 6 6 6 High 2 2.5 2 ttssuu SSeettuupp ttiimmee,, ddaattaa bbeeffoorree CCLLKK↑↑ nnss Low 2 2 2 High 2 2 2 tthh HHoolldd ttiimmee,, ddaattaa aafftteerr CCLLKK↑↑ nnss Low 2 2.5 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2−3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:12)(cid:19)(cid:20)(cid:17)(cid:17)(cid:15)(cid:19)(cid:15)(cid:16)(cid:9)(cid:16)(cid:18)(cid:12)(cid:21)(cid:22)(cid:15)(cid:9)(cid:5)(cid:14)(cid:20)(cid:22)(cid:18)(cid:5)(cid:14)(cid:10)(cid:22)(cid:1) (cid:23)(cid:20)(cid:12)(cid:24)(cid:9)(cid:6)(cid:18)(cid:1)(cid:12)(cid:13)(cid:12)(cid:15)(cid:9)(cid:10)(cid:25)(cid:12)(cid:22)(cid:25)(cid:12)(cid:1) SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993 switching characteristics (see Note 3) VCC = 5 V, VCC = 4.5 V to 5.5 V, CL = 50 pF, CL = 50 pF, FROM TO RL = 500 Ω, RL = 500Ω, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C TA = MIN to MAX† UNIT ′F374 SN54F374 SN74F374 MIN TYP MAX MIN MAX MIN MAX fmax 100 60 70 MHz tPLH 3.2 6.1 8.5 3.2 10.5 3.2 10 CCLLKK QQ nnss tPHL 3.2 6.1 8.5 3.2 11 3.2 10 tPZH 1.2 8.6 11.5 1.2 14 1.2 12.5 OOEE QQ nnss tPZL 1.2 5.4 7.5 1.2 10 1.2 8.5 tPHZ 1.2 4.9 7 1.2 8 1.2 8 OOEE QQ nnss tPLZ 1.2 3.9 5.5 1.2 7.5 1.2 6.5 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. 2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9759001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9759001Q2A SNJ54F 374FK 5962-9759001QRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9759001QR A SNJ54F374J 5962-9759001QRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9759001QR A SNJ54F374J 5962-9759001QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9759001QS A SNJ54F374W 5962-9759001QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9759001QS A SNJ54F374W JM38510/34105B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34105B2A JM38510/34105B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34105B2A JM38510/34105BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 34105BRA JM38510/34105BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 34105BRA JM38510/34105BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34105BSA JM38510/34105BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34105BSA M38510/34105B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34105B2A M38510/34105B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34105B2A M38510/34105BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 34105BRA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) M38510/34105BRA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 34105BRA M38510/34105BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34105BSA M38510/34105BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34105BSA SN54F374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54F374J SN54F374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54F374J SN74F374DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F374 & no Sb/Br) SN74F374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F374N (RoHS) SN74F374N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F374N (RoHS) SN74F374NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F374 & no Sb/Br) SN74F374NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F374 & no Sb/Br) SNJ54F374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9759001Q2A SNJ54F 374FK SNJ54F374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9759001Q2A Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SNJ54F 374FK SNJ54F374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9759001QR A SNJ54F374J SNJ54F374J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9759001QR A SNJ54F374J SNJ54F374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9759001QS A SNJ54F374W SNJ54F374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9759001QS A SNJ54F374W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54F374, SN74F374 : •Catalog: SN74F374 •Military: SN54F374 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74F374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74F374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74F374NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74F374DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74F374DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74F374NSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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