SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options Include Plastic SN54F109...J PACKAGE Small-Outline Packages, Ceramic Chip SN74F109...D OR N PACKAGE (TOP VIEW) Carriers, and Standard Plastic and Ceramic 300-mil DIPs 1CLR 1 16 VCC description 1J 2 15 2CLR 1K 3 14 2J These devices contain two independent J-K 1CLK 4 13 2K positive-edge-triggered flip-flops. A low level at 1PRE 5 12 2CLK the preset (PRE) or clear (CLR) inputs sets or 1Q 6 11 2PRE resets the outputs regardless of the levels of the 1Q 7 10 2Q other inputs. When PRE and CLR are inactive GND 8 9 2Q (high), data at the J and K input meeting the setup-time requirements are transferred to the SN54F109...FK PACKAGE outputs on the positive-going edge of the clock (TOP VIEW) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the R R L CL clock pulse. Following the hold time interval, data 1J 1CNC VC2C at the J and K inputs may be changed without affecting the levels at the outputs. These versatile 3 2 1 20 19 1K 4 18 2J flip-flops can perform as toggle flip-flops by 1CLK 5 17 2K grounding K and trying J high. They also can NC 6 16 NC perform as D-type flip-flops if J and K are tied 1PRE 7 15 2CLK together. 1Q 8 14 2PRE 9 10 11 12 13 The SN54F109 is characterized for operation over the full military temperature range of –55°C to QD C QQ 125°C. The SN74F109 is characterized for 1GN N 22 operation from 0°C to 70°C. NC – No internal connection FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H ↑ L L L H H H ↑ H L Toggle H H ↑ L H Q0 Q0 H H ↑ H H H L H H L X X Q0 Q0 †The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when PRE or CLR returns to its inactive (high) level. PRODUCTION DATA information is current as of publication date. Copyright  1993, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1

SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 logic symbol† 5 1PRE S 2 6 1J 1J 1Q 4 1CLK C1 3 7 1K 1K 1Q 1 1CLR R 11 2PRE 14 10 2J 2Q 12 2CLK 13 9 2K 2Q 15 2CLR †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V I Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V CC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range: SN54F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C SN74F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions SN54F109 SN74F109 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IIK Input clamp current –18 –18 mA IOH High-level output current –1 –1 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature –55 125 0 70 °C 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54F109 SN74F109 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V, IOH = –1 mA 2.5 3.4 2.5 3.4 VVOOHH VV VCC = 4.75 V, IOH = –1 mA 2.7 VOL VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A J, K, CLK –0.6 –0.6 IIIILL VVCCCC == 55.55 VV, VVII == 00.55 VV mmAA PRE or CLR –1.8 –1.8 IOS‡ VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA ICC VCC = 5.5 V, See Note 2 11.7 17 11.7 17 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with J, K, CLK, and PRE grounded then with J, K, CLK, and CLR grounded. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SN54F109 SN74F109 UUNNIITT ′F74 MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 100 0 70 0 90 MHz CLK high, PRE or CLR low 4 4 4 ttw PPuullssee dduurraattiioonn nnss CLK low 5 5 5 High 3 3 3 SSeettuupp ttiimmee, ddaattaa bbeeffoorree CCLLKK↑↑ tssuu Low 3 3 3 ns Setup time, inactive-state before CLK↑§ PRE or CLR to CLK 2 2 2 High 1 1 1 tthh HHoolldd ttiimmee, ddaattaa aafftteerr CCLLKK↑↑ nnss Low 1 1 1 §Inactive-state setup time is also referred to as recovery time. switching characteristics (see Note 3) VCC = 5 V, VCC = 4.5 V to 5.5 V, CL = 50 pF, CL = 50 pF, FROM TO RL = 500 W , RL = 500W , PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C TA = MIN to MAX¶ UNIT ′F109 SN54F109 SN74F109 MIN TYP MAX MIN MAX MIN MAX fmax 100 150 70 90 MHz tPLH 3 4.9 7 3 9 3 8 CCLLKK QQ oorr QQ nnss tPHL 3.6 5.8 8 3.6 10.5 3.6 9.2 tPLH 2.4 4.8 7 2.4 9 2.4 8 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 2.7 6.6 9 2.7 11.5 2.7 10.5 ¶For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9758001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9758001Q2A SNJ54F 109FK 5962-9758001QEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758001QE A SNJ54F109J 5962-9758001QFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758001QF A SNJ54F109W JM38510/34102B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34102B2A JM38510/34102BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34102BEA JM38510/34102BFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34102BFA M38510/34102B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 34102B2A M38510/34102BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34102BEA M38510/34102BFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 34102BFA SN74F109D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F109 & no Sb/Br) SN74F109DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F109 & no Sb/Br) SN74F109N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74F109N & no Sb/Br) SNJ54F109FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9758001Q2A SNJ54F 109FK SNJ54F109J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758001QE A SNJ54F109J Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SNJ54F109W ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758001QF A SNJ54F109W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54F109, SN74F109 : Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: SN74F109 •Military: SN54F109 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) SN74F109DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74F109DR SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

None

None

None

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated