(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:12) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:10)(cid:12)(cid:16)(cid:6)(cid:20)(cid:7) (cid:10)(cid:16)(cid:14)(cid:21)(cid:16)(cid:12) (cid:21)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26)(cid:27)(cid:28)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26) (cid:15)(cid:20)(cid:7)(cid:29) (cid:20)(cid:2)(cid:7)(cid:19)(cid:26)(cid:2)(cid:17)(cid:8) (cid:24)(cid:23)(cid:8)(cid:8)(cid:28)(cid:14)(cid:15)(cid:2) (cid:26)(cid:19)(cid:1)(cid:20)(cid:1)(cid:7)(cid:14)(cid:26)(cid:1) SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 (cid:1) Member of the Texas Instruments DGG, DGV, OR DL PACKAGE Widebus Family (TOP VIEW) (cid:1) 4-Ω Switch Connection Between Two Ports S 1 56 NC (cid:1) Rail-to-Rail Switching on Data I/O Ports 1A 2 55 NC (cid:1) Ioff Supports Partial-Power-Down Mode NC 3 54 1B1 Operation 2A 4 53 1B2 (cid:1) Make-Before-Break Feature NC 5 52 2B1 (cid:1) Internal 500-Ω Pulldown Resistors to 3A 6 51 2B2 Ground NC 7 50 3B1 (cid:1) GND 8 49 GND Latch-Up Performance Exceeds 250 mA Per 4A 9 48 3B2 JESD 17 NC 10 47 4B1 description/ordering information 5A 11 46 4B2 NC 12 45 5B1 The SN74CBTLV16292 is a 12-bit 1-of-2 6A 13 44 5B2 high-speed FET multiplexer/demultiplexer. The NC 14 43 6B1 low on-state resistance of the switch allows 7A 15 42 6B2 connections to be made with minimal propagation NC 16 41 7B1 delay. VCC 17 40 7B2 8A 18 39 8B1 When the select (S) input is low, port A is connected to port B1, and R is connected to GND 19 38 GND INT port B2. When S is high, port A is connected to NC 20 37 8B2 port B2, and R is connected to port B1. 9A 21 36 9B1 INT NC 22 35 9B2 This device is fully specified for 10A 23 34 10B1 partial-power-down applications using I . The I off off NC 24 33 10B2 feature ensures that damaging current will not 11A 25 32 11B1 backflow through the device when it is powered NC 26 31 11B2 down. The device has isolation during power off. 12A 27 30 12B1 NC 28 29 12B2 NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CBTLV16292DL SSSSOOPP −− DDLL CCBBTTLLVV1166229922 Tape and reel SN74CBTLV16292DLR −−4400°°CC ttoo 8855°°CC TSSOP − DGG Tape and reel SN74CBTLV16292GR CBTLV16292 TVSOP − DGV Tape and reel SN74CBTLV16292VR CN292 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:24)(cid:26)(cid:14)(cid:28)(cid:23)(cid:5)(cid:7)(cid:20)(cid:14)(cid:2) (cid:28)(cid:17)(cid:7)(cid:17) (cid:30)(cid:31)!"#$%&(cid:30)"(cid:31) (cid:30)’ ()##*(cid:31)& %’ "! +),-(cid:30)(%&(cid:30)"(cid:31) .%&*/ Copyright  2003, Texas Instruments Incorporated (cid:24)#".)(&’ ("(cid:31)!"#$ &" ’+*((cid:30)!(cid:30)(%&(cid:30)"(cid:31)’ +*# &0* &*#$’ "! (cid:7)*1%’ (cid:20)(cid:31)’&#)$*(cid:31)&’ ’&%(cid:31).%#. 2%##%(cid:31)&3/ (cid:24)#".)(&(cid:30)"(cid:31) +#"(*’’(cid:30)(cid:31)4 ."*’ (cid:31)"& (cid:31)*(*’’%#(cid:30)-3 (cid:30)(cid:31)(-).* &*’&(cid:30)(cid:31)4 "! %-- +%#%$*&*#’/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:12) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:10)(cid:12)(cid:16)(cid:6)(cid:20)(cid:7) (cid:10)(cid:16)(cid:14)(cid:21)(cid:16)(cid:12) (cid:21)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26)(cid:27)(cid:28)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26) (cid:15)(cid:20)(cid:7)(cid:29) (cid:20)(cid:2)(cid:7)(cid:19)(cid:26)(cid:2)(cid:17)(cid:8) (cid:24)(cid:23)(cid:8)(cid:8)(cid:28)(cid:14)(cid:15)(cid:2) (cid:26)(cid:19)(cid:1)(cid:20)(cid:1)(cid:7)(cid:14)(cid:26)(cid:1) SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 FUNCTION TABLE INPUT FUNCTION S A port = B1 port L RINT = B2 port A port = B2 port H RINT = B1 port logic diagram (positive logic) 2 54 1A SW 1B1 RINT RINT 53 SW 1B2 27 30 12A SW 12B1 RINT RINT 29 SW 12B2 1 S 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:12) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:10)(cid:12)(cid:16)(cid:6)(cid:20)(cid:7) (cid:10)(cid:16)(cid:14)(cid:21)(cid:16)(cid:12) (cid:21)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26)(cid:27)(cid:28)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26) (cid:15)(cid:20)(cid:7)(cid:29) (cid:20)(cid:2)(cid:7)(cid:19)(cid:26)(cid:2)(cid:17)(cid:8) (cid:24)(cid:23)(cid:8)(cid:8)(cid:28)(cid:14)(cid:15)(cid:2) (cid:26)(cid:19)(cid:1)(cid:20)(cid:1)(cid:7)(cid:14)(cid:26)(cid:1) SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W JA DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VCC = 2.3 V to 2.7 V 1.7 VVIIHH HHiigghh--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 2 VCC = 2.3 V to 2.7 V 0.7 VVIILL LLooww--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 0.8 TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:12) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:10)(cid:12)(cid:16)(cid:6)(cid:20)(cid:7) (cid:10)(cid:16)(cid:14)(cid:21)(cid:16)(cid:12) (cid:21)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26)(cid:27)(cid:28)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26) (cid:15)(cid:20)(cid:7)(cid:29) (cid:20)(cid:2)(cid:7)(cid:19)(cid:26)(cid:2)(cid:17)(cid:8) (cid:24)(cid:23)(cid:8)(cid:8)(cid:28)(cid:14)(cid:15)(cid:2) (cid:26)(cid:19)(cid:1)(cid:20)(cid:1)(cid:7)(cid:14)(cid:26)(cid:1) SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 3 V, II = −18 mA −1.2 V II VCC = 3.6 V, VI = VCC or GND ±1 µA Ioff VCC = 0, VI or VO = 0 to 3.6 V 10 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA ∆ICC‡ Control input VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA Ci Control input VI = 3.3 V or 0 3.5 pF Cio A or B port VO = 3.3 V or 0 22.5 pF II = 64 mA 5 8 VVCCCC == 22..33 VV,, VVII == 00 II = 24 mA 5 8 TTYYPP aatt VVCCCC == 22..55 VV VI = 1.7 V, II = 15 mA 11 40 rroonn§§ ΩΩ II = 64 mA 3 7 VVII == 00 VVCCCC == 33 VV II = 24 mA 3 7 VI = 2.4 V, II = 15 mA 7 15 †All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. §Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR FROM TO ± 0.2 V ± 0.3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd¶ A or B B or A 0.15 0.25 ns tpd# S A 2.5 7.1 2.5 6.7 ns ten S B 1 5.6 1 5 ns tdis S B 1 5 1 4.5 ns ¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). #This propagation delay was measured by observing the change of voltage on the A output introduced by static levels equal to 3-V or 0 for 3.3 V ± 0.3 V or VCC or 0 for 2.5 V ± 0.2 V on B1 and B2 to achieve the desired transition. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR DDEESSCCRRIIPPTTIIOONN ± 0.2 V ± 0.3 V UUNNIITT MIN MAX MIN MAX tmbb|| Make-before-break time 0 2 0 2 ns ||The make-before-break time is the time interval between make and break, during the transition from one selected port to the other. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:12) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:10)(cid:12)(cid:16)(cid:6)(cid:20)(cid:7) (cid:10)(cid:16)(cid:14)(cid:21)(cid:16)(cid:12) (cid:21)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26)(cid:27)(cid:28)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:20)(cid:24)(cid:8)(cid:19)(cid:25)(cid:19)(cid:26) (cid:15)(cid:20)(cid:7)(cid:29) (cid:20)(cid:2)(cid:7)(cid:19)(cid:26)(cid:2)(cid:17)(cid:8) (cid:24)(cid:23)(cid:8)(cid:8)(cid:28)(cid:14)(cid:15)(cid:2) (cid:26)(cid:19)(cid:1)(cid:20)(cid:1)(cid:7)(cid:14)(cid:26)(cid:1) SCDS055K − MARCH 1998 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output RL S1 Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC tPHZ/tPZH GND CL (see Note A) RL VCC CL RL V∆ 2.5 V ±0.2 V 30 pF 500 Ω 0.15 V 3.3 V ±0.3 V 50 pF 500 Ω 0.3 V LOAD CIRCUIT VCC Timing Input VCC/2 0 V tw tsu th VCC VCC Input VCC/2 VCC/2 Data Input VCC/2 VCC/2 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input VCC/2 VCC/2 VCC/2 VCC/2 Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VCC Output VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + V∆ VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output VOH Waveform 2 VOH Output VCC/2 VCC/2 S1 at GND VCC/2 VOH − V∆ VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBTLV16292DL ACTIVE SSOP DL 56 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 & no Sb/Br) SN74CBTLV16292DLR ACTIVE SSOP DL 56 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 & no Sb/Br) SN74CBTLV16292GR ACTIVE TSSOP DGG 56 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16292 & no Sb/Br) SN74CBTLV16292VR ACTIVE TVSOP DGV 56 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CN292 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBTLV16292DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74CBTLV16292GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74CBTLV16292VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBTLV16292DLR SSOP DL 56 1000 367.0 367.0 55.0 SN74CBTLV16292GR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74CBTLV16292VR TVSOP DGV 56 2000 367.0 367.0 45.0 PackMaterials-Page2

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 SEATING PLANE TYP 7.9 A PIN 1 ID 0.1 C AREA 54X 0.5 56 1 14.1 2X 13.9 13.5 NOTE 3 28 29 0.27 B 6.2 56X 0.17 1.2 MAX 6.0 0.08 C A B (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated