(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:10)(cid:10) (cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:13)(cid:8)(cid:7)(cid:16)(cid:17)(cid:18) (cid:12)(cid:4)(cid:15)(cid:6)(cid:19)(cid:7) (cid:20)(cid:18)(cid:7) (cid:6)(cid:21)(cid:1) (cid:1)(cid:14)(cid:19)(cid:7)(cid:5)(cid:22) SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003 (cid:1) Member of the Texas Instruments DGG, DGV, OR DL PACKAGE Widebus Family (TOP VIEW) (cid:1) 5-Ω Switch Connection Between Two Ports NC 1 56 1OE (cid:1) Rail-to-Rail Switching on Data I/O Ports 1A1 2 55 2OE (cid:1) Ioff Supports Partial-Power-Down Mode 1A2 3 54 1B1 Operation 1A3 4 53 1B2 (cid:1) Latch-Up Performance Exceeds 250 mA Per 1A4 5 52 1B3 JESD 17 1A5 6 51 1B4 (cid:1) 1A6 7 50 1B5 ESD Protection Exceeds JESD 22 GND 8 49 GND − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) 1A7 9 48 1B6 1A8 10 47 1B7 description/ordering information 1A9 11 46 1B8 1A10 12 45 1B9 The SN74CBTLV16211 provides 24 bits of 1A11 13 44 1B10 high-speed bus switching. The low on-state 1A12 14 43 1B11 resistance of the switch allows connections to be 2A1 15 42 1B12 made with minimal propagation delay. 2A2 16 41 2B1 The device is organized as dual 12-bit bus VCC 17 40 2B2 switches with separate output-enable (OE) 2A3 18 39 2B3 inputs. It can be used as two 12-bit bus switches GND 19 38 GND or as one 24-bit bus switch. When OE is low, the 2A4 20 37 2B4 associated 12-bit bus switch is on, and port A is 2A5 21 36 2B5 connected to port B. When OE is high, the switch 2A6 22 35 2B6 is open, and the high-impedance state exists 2A7 23 34 2B7 between the two ports. 2A8 24 33 2B8 2A9 25 32 2B9 This device is fully specified for 2A10 26 31 2B10 partial-power-down applications using I . The I off off 2A11 27 30 2B11 feature ensures that damaging current will not 2A12 28 29 2B12 backflow through the device when it is powered down. The device has isolation during power off. NC − No internal connection To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CBTLV16211DL SSSSOOPP −− DDLL CCBBTTLLVV1166221111 Tape and reel SN74CBTLV16211DLR −−4400°°CC ttoo 8855°°CC TSSOP − DGG Tape and reel SN74CBTLV16211GR CBTLV16211 TVSOP − DGV Tape and reel SN74CBTLV16211VR CN211 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:23)(cid:24)(cid:13)(cid:25)(cid:21)(cid:5)(cid:7)(cid:19)(cid:13)(cid:2) (cid:25)(cid:16)(cid:7)(cid:16) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2003, Texas Instruments Incorporated (cid:23)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:7)&-!# (cid:19)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:23)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:10)(cid:10) (cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:13)(cid:8)(cid:7)(cid:16)(cid:17)(cid:18) (cid:12)(cid:4)(cid:15)(cid:6)(cid:19)(cid:7) (cid:20)(cid:18)(cid:7) (cid:6)(cid:21)(cid:1) (cid:1)(cid:14)(cid:19)(cid:7)(cid:5)(cid:22) SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003 FUNCTION TABLE (each 12-bit bus switch) INPUT FUNCTION OE L A port = B port H Disconnect logic diagram (positive logic) 2 54 1A1 SW 1B1 14 42 1A12 SW 1B12 56 1OE 15 41 2A1 SW 2B1 28 29 2A12 SW 2B12 55 2OE simplified schematic, each FET switch A B (OE) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:10)(cid:10) (cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:13)(cid:8)(cid:7)(cid:16)(cid:17)(cid:18) (cid:12)(cid:4)(cid:15)(cid:6)(cid:19)(cid:7) (cid:20)(cid:18)(cid:7) (cid:6)(cid:21)(cid:1) (cid:1)(cid:14)(cid:19)(cid:7)(cid:5)(cid:22) SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W JA DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VCC = 2.3 V to 2.7 V 1.7 VVIIHH HHiigghh--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 2 VCC = 2.3 V to 2.7 V 0.7 VVIILL LLooww--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 0.8 TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:10)(cid:10) (cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:13)(cid:8)(cid:7)(cid:16)(cid:17)(cid:18) (cid:12)(cid:4)(cid:15)(cid:6)(cid:19)(cid:7) (cid:20)(cid:18)(cid:7) (cid:6)(cid:21)(cid:1) (cid:1)(cid:14)(cid:19)(cid:7)(cid:5)(cid:22) SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 3 V, II = −18 mA −1.2 V II VCC = 3.6 V, VI = VCC or GND ±1 µA Ioff VCC = 0, VI or VO = 0 to 3.6 V 10 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA ∆ICC‡ Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA Ci Control inputs VI = 3.3 V or 0 4.5 pF Cio(OFF) VO = 3.3 V or 0, OE = VCC 6.5 pF II = 64 mA 5 8 VVCCCC == 22..33 VV,, VVII == 00 II = 24 mA 5 8 TTYYPP aatt VVCCCC == 22..55 VV VI = 1.7 V, II = 15 mA 27 40 rroonn§§ ΩΩ II = 64 mA 5 7 VVII == 00 VVCCCC == 33 VV II = 24 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 †All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. §Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR FROM TO ± 0.2 V ± 0.3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd¶ A or B B or A 0.15 0.25 ns ten OE A or B 1 7 1 6.2 ns tdis OE A or B 1 7.2 1 7.7 ns ¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:10)(cid:10) (cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:13)(cid:8)(cid:7)(cid:16)(cid:17)(cid:18) (cid:12)(cid:4)(cid:15)(cid:6)(cid:19)(cid:7) (cid:20)(cid:18)(cid:7) (cid:6)(cid:21)(cid:1) (cid:1)(cid:14)(cid:19)(cid:7)(cid:5)(cid:22) SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output RL S1 Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC tPHZ/tPZH GND CL (see Note A) RL VCC CL RL V∆ 2.5 V ±0.2 V 30 pF 500 Ω 0.15 V 3.3 V ±0.3 V 50 pF 500 Ω 0.3 V LOAD CIRCUIT VCC Timing Input VCC/2 0 V tw tsu th VCC VCC Input VCC/2 VCC/2 Data Input VCC/2 VCC/2 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input VCC/2 VCC/2 VCC/2 VCC/2 Control 0 V 0 V tPLH tPHL Output tPZL tPLZ VOH Waveform 1 VCC Output VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + V∆ VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output VOH Waveform 2 VOH Output VCC/2 VCC/2 S1 at GND VCC/2 VOH − V∆ VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 74CBTLV16211DLG4 ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBTLV16211DLRG4 ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBTLV16211GRE4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBTLV16211GRG4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBTLV16211VRE4 ACTIVE TVSOP DGV 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBTLV16211VRG4 ACTIVE TVSOP DGV 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBTLV16211DL ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBTLV16211DLR ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBTLV16211GR ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBTLV16211VR ACTIVE TVSOP DGV 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) SN74CBTLV16211DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74CBTLV16211GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74CBTLV16211VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBTLV16211DLR SSOP DL 56 1000 346.0 346.0 49.0 SN74CBTLV16211GR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74CBTLV16211VR TVSOP DGV 56 2000 346.0 346.0 41.0 PackMaterials-Page2

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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