(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 (cid:1) (cid:1) Undershoot Protection for Off-Isolation on Data I/Os Support 0 to 5-V Signaling Levels A and B Ports Up To −2 V (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) (cid:1) (cid:1) Integrated Diode to V Provides 5-V Input Control Inputs Can be Driven by TTL or CC Down To 3.3-V Output Level Shift 5-V/3.3-V CMOS Outputs (cid:1) (cid:1) Bidirectional Data Flow, With Near-Zero I Supports Partial-Power-Down Mode off Propagation Delay Operation (cid:1) (cid:1) Low ON-State Resistance (r ) Latch-Up Performance Exceeds 100 mA Per on Characteristics (r = 3 Ω Typical) JESD 78, Class II on (cid:1) (cid:1) Low Input/Output Capacitance Minimizes ESD Performance Tested Per JESD 22 Loading and Signal Distortion − 2000-V Human-Body Model (C = 5 pF Typical) (A114-B, Class II) io(OFF) (cid:1) Data and Control Inputs Provide − 1000-V Charged-Device Model (C101) (cid:1) Undershoot Clamp Diodes Supports Both Digital and Analog (cid:1) V Operating Range From 4.5 V to 5.5 V Applications: USB Interface, Memory CC Interleaving, Bus Isolation, Low-Distortion Signal Gating D OR PW PACKAGE (TOP VIEW) 1OE 1 8 VCC 1A 2 7 2OE 1B 3 6 2B GND 4 5 2A description/ordering information The SN74CBTD3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ), on allowing for minimal propagation delay. This device features an integrated diode in series with V to provide CC level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3306C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBTD3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CBTD3306CD SSOOIICC −− DD CCCC330066CC Tape and reel SN74CBTD3306CDR −−4400°°CC ttoo 8855°°CC Tube SN74CBTD3306CPW TTSSSSOOPP −− PPWW CCCC330066CC Tape and reel SN74CBTD3306CPWR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:28)(cid:26)(cid:27)(cid:8)(cid:12)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) (cid:8)(cid:13)(cid:7)(cid:13) (cid:29)(cid:30)(cid:31)!"#$%(cid:29)!(cid:30) (cid:29)& ’("")(cid:30)% $& !(cid:31) *(+,(cid:29)’$%(cid:29)!(cid:30) -$%). Copyright  2003, Texas Instruments Incorporated (cid:28)"!-(’%& ’!(cid:30)(cid:31)!"# %! &*)’(cid:29)(cid:31)(cid:29)’$%(cid:29)!(cid:30)& *)" %/) %)"#& !(cid:31) (cid:7))0$& (cid:18)(cid:30)&%"(#)(cid:30)%& &%$(cid:30)-$"- 1$""$(cid:30)%2. (cid:28)"!-(’%(cid:29)!(cid:30) *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 description/ordering information (continued) This device is fully specified for partial-power-down applications using I . The I feature ensures that off off damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each bus switch) IINNPPUUTT IINNPPUUTT//OOUUTTPPUUTT FFUUNNCCTTIIOONN OE A L B A port = B port H Z Disconnect logic diagram (positive logic) 2 3 1A SW 1B 1 1OE 5 6 2A SW 2B 7 2OE simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† †EN is the internal enable signal applied to the switch. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V IN Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I/O Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through V or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W JA PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Notes 6 and 7) MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level control input voltage 2 5.5 V VIL Low-level control input voltage 0 0.8 V VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTES: 6. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7. In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Control inputs VCC = 4.5 V, IIN = −18 mA −1.8 V 0 mA > II ≥ −50 mA, VIKU Data inputs VCC = 5 V, VIN = VCC or GND, Switch OFF −2 V VOH See Figures 4 and 5 IIN Control inputs VCC = 5.5 V, VIN = VCC or GND ±1 µA IOZ‡ VCC = 5.5 V, VVIO = = 0 0, to 5.5 V, SVIwNit c=h V OCFCF ,or GND ±10 µA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA II/O = 0, ICC VCC = 5.5 V, VIN = VCC or GND, Switch ON or OFF 1.5 mA ∆ICC§ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Cin Control inputs VIN = 3 V or 0 3.5 pF Cio(OFF) VI/O = 3 V or 0, Switch OFF, VIN = VCC or GND 5 pF Cio(ON) VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 12.5 pF IO = 64 mA 3 6 rroonn¶ VVCCCC == 44..55 VV VVII == 00 IO = 30 mA 3 6 Ω VI = 2.4 V, IO = −15 mA 9 20 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡For I/O ports, the parameter IOZ includes the input leakage current. §This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 5 V PPAARRAAMMEETTEERR FROM TO ± 0.5 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX tpd# A or B B or A 0.15 ns ten OE A or B 1.5 4.7 ns tdis OE A or B 1.5 4.7 ns #The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOUTU VCC = 5.5 V, Switch OFF, VIN = VCC or GND 2 VOH−0.3 V †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC 11 V 5.5 V Input 100 kΩ Input 90 % 90 % Generator 50 Ω (Open 2 ns 2 ns DUT Socket) Ax Bx 10 % 10 % −2 V 100 kΩ 10 pF 20 ns VS Output VOH (VOUTU) VOH − 0.3 Figure 1. Device Test Setup Figure 2. Transient Input Voltage (V) and Output I Voltage (V ) Waveforms OUTU (Switch OFF) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION FOR LEVEL SHIFTER VCC Input Generator VIN 50 Ω VG1 50 Ω TEST CIRCUIT DUT 7 V Input Generator S1 VI VO RL Open 50 Ω GND VG2 50 Ω CL RL (see Note A) TEST VCC S1 RL VI CL V∆ tpd(s) 5 V ±0.5 V Open 500 Ω VCC or GND 50 pF tPLZ/tPZL 5 V ±0.5 V 7 V 500 Ω GND 50 pF 0.3 V tPHZ/tPZH 5 V ±0.5 V Open 500 Ω VCC 50 pF 0.3 V Output 3 V Control 1.5 V 1.5 V (VIN) 0 V tPZL tPLZ Output 3.5 V Output 3 V Waveform 1 1.5 V Control 1.5 V 1.5 V S1 at 7 V VOL + V∆ (VIN) 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − V∆ Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH OUTPUT VOLTAGE HIGH vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 4 4 TA = 85°C TA = 25°C 3.75 VI = VCC 100 µA 3.75 VI = VCC 3.5 6 mA 3.5 100 µA V V − 12 mA − gh 3.25 24 mA gh 3.25 612 m mAA Hi Hi ge 3 ge 3 24 mA a a olt 2.75 olt 2.75 V V ut ut utp 2.5 utp 2.5 O O − 2.25 − 2.25 H H VO 2 V O 2 1.75 1.75 1.5 1.5 4.5 4.75 5 5.25 5.5 5.75 4.5 4.75 5 5.25 5.5 5.75 VCC − Supply Voltage − V VCC − Supply Voltage − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 TA = 0°C 3.75 VI = VCC 3.5 V 100 µA − h 3.25 6 mA g Hi 12 mA e 3 g 24 mA a olt 2.75 V ut p 2.5 ut O − 2.25 H O V 2 1.75 1.5 4.5 4.75 5 5.25 5.5 5.75 VCC − Supply Voltage − V Figure 4. V Values OH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:9)(cid:10)(cid:11)(cid:5) (cid:8)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:7) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:14)(cid:16)(cid:20)(cid:16)(cid:14) (cid:1)(cid:19)(cid:18)(cid:15)(cid:7)(cid:18)(cid:2)(cid:21) (cid:22)(cid:23)(cid:20) (cid:6)(cid:12)(cid:1) (cid:1)(cid:17)(cid:18)(cid:7)(cid:5)(cid:19) (cid:17)(cid:18)(cid:7)(cid:19) (cid:24)(cid:25)(cid:23)(cid:20) (cid:12)(cid:2)(cid:8)(cid:16)(cid:26)(cid:1)(cid:19)(cid:27)(cid:27)(cid:7) (cid:28)(cid:26)(cid:27)(cid:7)(cid:16)(cid:5)(cid:7)(cid:18)(cid:27)(cid:2) SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs INPUT VOLTAGE 3.5 VCC = 5 V 100 µA TA = 25°C 6 mA 3 12 mA 24 mA 2.5 V − e g a 2 olt V ut 1.5 p ut O − O 1 V 5 0 0 1 2 3 4 5 VI − Input Voltage − V Figure 5. Data Output Voltage vs Data Input Voltage 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBTD3306CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CC306C & no Sb/Br) SN74CBTD3306CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CC306C & no Sb/Br) SN74CBTD3306CPW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CC306C & no Sb/Br) SN74CBTD3306CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 CC306C & no Sb/Br) SN74CBTD3306CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CC306C & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBTD3306CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBTD3306CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 SN74CBTD3306CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 SN74CBTD3306CPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBTD3306CDR SOIC D 8 2500 340.5 338.1 20.6 SN74CBTD3306CPWR TSSOP PW 8 2000 367.0 367.0 35.0 SN74CBTD3306CPWR TSSOP PW 8 2000 364.0 364.0 27.0 SN74CBTD3306CPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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