(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 (cid:1) Undershoot Protection for Off-Isolation on D, DB, DBQ, OR PW PACKAGE A and B Ports Up To −2 V (TOP VIEW) (cid:1) Bidirectional Data Flow, With Near-Zero Propagation Delay S 1 16 VCC (cid:1) 1B1 2 15 OE Low ON-State Resistance (r ) on 1B2 3 14 4B1 Characteristics (r = 3 Ω Typical) on 1A 4 13 4B2 (cid:1) Low Input/Output Capacitance Minimizes 2B1 5 12 4A Loading and Signal Distortion 2B2 6 11 3B1 (C = 5.5 pF Typical) io(OFF) 2A 7 10 3B2 (cid:1) Data and Control Inputs Provide GND 8 9 3A Undershoot Clamp Diodes (cid:1) Low Power Consumption (I = 3 µA Max) RGY PACKAGE CC (TOP VIEW) (cid:1) V Operating Range From 4 V to 5.5 V CC C (cid:1) Data I/Os Support 0 to 5-V Signaling Levels S VC (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) 1 16 (cid:1) Control Inputs Can be Driven by TTL or 1B1 2 15 OE 5-V/3.3-V CMOS Outputs 1B2 3 14 4B1 (cid:1) I Supports Partial-Power-Down Mode 1A 4 13 4B2 off Operation 2B1 5 12 4A (cid:1) 2B2 6 11 3B1 Latch-Up Performance Exceeds 100 mA Per 2A 7 10 3B2 JESD 78, Class II 8 9 (cid:1) ESD Performance Tested Per JESD 22 D A − 2000-V Human-Body Model N 3 G (A114-B, Class II) − 1000-V Charged-Device Model (C101) (cid:1) Supports I2C Bus Expansion (cid:1) Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating description/ordering information ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74CBT3257CRGYR CU257C Tube SN74CBT3257CD SSOOIICC −− DD CCBBTT33225577CC Tape and reel SN74CBT3257CDR −−4400°CC ttoo 8855°CC SSOP − DB Tape and reel SN74CBT3257CDBR CU257C SSOP (QSOP) − DBQ Tape and reel SN74CBT3257CDBQR CU257C Tube SN74CBT3257CPW TTSSSSOOPP −− PPWW CCUU225577CC Tape and reel SN74CBT3257CPWR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:20)(cid:22)(cid:14)(cid:24)(cid:18)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) (cid:24)(cid:29)(cid:7)(cid:29) (cid:30)(cid:31)!"#$%&(cid:30)"(cid:31) (cid:30)’ ()##*(cid:31)& %’ "! +),-(cid:30)(%&(cid:30)"(cid:31) .%&*/ Copyright  2003, Texas Instruments Incorporated (cid:20)#".)(&’ ("(cid:31)!"#$ &" ’+*((cid:30)!(cid:30)(%&(cid:30)"(cid:31)’ +*# &0* &*#$’ "! (cid:7)*1%’ (cid:12)(cid:31)’&#)$*(cid:31)&’ ’&%(cid:31).%#. 2%##%(cid:31)&3/ (cid:20)#".)(&(cid:30)"(cid:31) +#"(*’’(cid:30)(cid:31)4 ."*’ (cid:31)"& (cid:31)*(*’’%#(cid:30)-3 (cid:30)(cid:31)(-).* &*’&(cid:30)(cid:31)4 "! %-- +%#%$*&*#’/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 description/ordering information (continued) The SN74CBT3257C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and on B ports of the SN74CBT3257C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT3257C is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) input controls the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using I . The I feature ensures that off off damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS IINNPPUUTT//OOUUTTPPUUTT FFUUNNCCTTIIOONN OE S1 A L L B1 A port = B1 port L H B2 A port = B2 port H X Z Disconnect 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 logic diagram (positive logic) 4 2 1A SW 1B1 3 SW 1B2 7 5 2A SW 2B1 6 SW 2B2 9 11 3A SW 3B1 10 SW 3B2 12 14 4A SW 4B1 13 SW 4B2 1 S 15 OE simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† †EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V IN Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I/O Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA I/O Continuous current through V or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 7) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 5.5 V VIL Low-level control input voltage 0 0.8 V VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Control inputs VCC = 4.5 V, IIN = −18 mA −1.8 V 0 mA > II ≥ −50 mA, VIKU Data inputs VCC = 5 V, VIN = VCC or GND, Switch OFF −2 V IIN Control inputs VCC = 5.5 V, VIN = VCC or GND ±1 µA IOZ‡ VCC = 5.5 V, VVIO = = 0 0, to 5.5 V, SVIwNit c=h V OCFCF ,or GND ±10 µA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA ICC VCC = 5.5 V, IVI/ION == 0V,CC or GND, Switch ON or OFF 3 µA ∆ICC§ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Cin Control inputs VIN = 3 V or 0 3.5 pF A port 8.5 pF CCiioo((OOFFFF)) VVII//OO == 33 VV oorr 00,, SSwwiittcchh OOFFFF,, VVIINN == VVCCCC oorr GGNNDD B port 5.5 pF Cio(ON) VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 16.5 pF VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, IO = −15 mA 8 12 rroonn¶¶ IO = 64 mA 3 6 ΩΩ VVII == 00 VVCCCC == 44..55 VV IO = 30 mA 3 6 VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡For I/O ports, the parameter IOZ includes the input leakage current. §This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 3) VCC = 5 V PPAARRAAMMEETTEERR FROM TO VCC = 4 V ± 0.5 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd# A or B B or A 0.24 0.15 ns tpd(s) S A 6 1.5 5.6 ns S B 6.3 1.5 5.8 tteenn nnss OE A or B 6.3 1.5 5.8 S B 6.5 1.5 6 ttddiiss nnss OE A or B 5.9 1.5 5.9 #The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOUTU VCC = 5.5 V, Switch OFF, VIN = VCC or GND 2 VOH−0.3 V †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC 11 V 5.5 V Input 100 kΩ Input 90 % 90 % Generator 50 Ω (Open 2 ns 2 ns DUT Socket) Ax Bx 10 % 10 % −2 V 100 kΩ 10 pF 20 ns VS Output VOH (VOUTU) VOH − 0.3 Figure 1. Device Test Setup Figure 2. Transient Input Voltage (V) and Output I Voltage (V ) Waveforms OUTU (Switch OFF) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:3)(cid:5) (cid:4)(cid:11)(cid:6)(cid:12)(cid:7) (cid:13)(cid:11)(cid:14)(cid:15)(cid:11)(cid:9) (cid:15)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:10)(cid:11)(cid:25) (cid:6)(cid:18)(cid:1) (cid:1)(cid:26)(cid:12)(cid:7)(cid:5)(cid:27) (cid:26)(cid:12)(cid:7)(cid:27) (cid:28)(cid:9)(cid:11)(cid:25) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:27)(cid:14)(cid:14)(cid:7) (cid:20)(cid:22)(cid:14)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:14)(cid:2) SCDS137 − OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω VG1 50 Ω TEST CIRCUIT DUT 7 V Input Generator VI VO RL S1 Open 50 Ω GND VG2 50 Ω CL RL (see Note A) TEST VCC S1 RL VI CL V∆ tpd(s) 5 V ±0.5 V Open 500 Ω VCC or GND 50 pF 4 V Open 500 Ω VCC or GND 50 pF 5 V ±0.5 V 7 V 500 Ω GND 50 pF 0.3 V tPLZ/tPZL 4 V 7 V 500 Ω GND 50 pF 0.3 V tPHZ/tPZH 5 V ±0.5 V Open 500 Ω VCC 50 pF 0.3 V 4 V Open 500 Ω VCC 50 pF 0.3 V Output 3 V Control 1.5 V 1.5 V (VIN) 0 V tPZL tPLZ Output 3.5 V Output 3 V Waveform 1 1.5 V Control 1.5 V 1.5 V S1 at 7 V VOL + V∆ (VIN) 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − V∆ Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBT3257CD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3257C & no Sb/Br) SN74CBT3257CDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU257C & no Sb/Br) SN74CBT3257CDBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3257C & no Sb/Br) SN74CBT3257CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3257C & no Sb/Br) SN74CBT3257CPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU257C & no Sb/Br) SN74CBT3257CRGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU257C & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBT3257CDBQR SSOP DBQ 16 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBT3257CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74CBT3257CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBT3257CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBT3257CPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBT3257CRGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT3257CDBQR SSOP DBQ 16 2500 340.5 338.1 20.6 SN74CBT3257CDR SOIC D 16 2500 333.2 345.9 28.6 SN74CBT3257CPWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74CBT3257CPWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74CBT3257CPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74CBT3257CRGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 14X .0250 [0.635] 16 1 2X .189-.197 .175 [4.81-5.00] [4.45] NOTE 3 8 9 16X .008-.012 B .150-.157 [0.21-0.30] .069 MAX [3.81-3.98] [1.75] NOTE 4 .007 [0.17] C A B .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 0 - 8 [0.11-0.25] .016-.035 [0.41-0.88] DETAIL A (.041 ) TYPICAL [1.04] 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com

EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM SEE DETAILS 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 8 9 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL .002 MAX .002 MIN [0.05] [0.05] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 8 9 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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