SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 FEATURES • SN74CBT3253CFunctionallyIdenticalto Industry-Standard’3253Function • UndershootProtectionforOff-IsolationonA andBPortsupto–2V • BidirectionalDataFlow,WithNear-Zero PropagationDelay • LowON-StateResistance(r )Characteristics on (r =3W Typical) on • LowInput/OutputCapacitanceMinimizes LoadingandSignalDistortion (C =5.5pFTypical) io(OFF) • DataandControlInputsProvideUndershoot ClampDiodes • LowPowerConsumption(I =3m AMax) CC • V OperatingRangeFrom4Vto5.5V CC • DataI/OsSupport0to5-VSignalingLevels (0.8V,1.2V,1.5V,1.8V,2.5V,3.3V,5V) • ControlInputsCanBeDrivenbyTTLor 5-V/3.3-VCMOSOutputs • I SupportsPartial-Power-DownMode off Operation • Latch-UpPerformanceExceeds100mAPer JESD78,ClassII • ESDPerformanceTestedPerJESD22 – 2000-VHuman-BodyModel (A114-B,ClassII) – 1000-VCharged-DeviceModel(C101) • SupportsI2CBusExpansion • SupportsBothDigitalandAnalog Applications:USBInterface,BusIsolation, Low-DistortionSignalGating DESCRIPTION/ORDERING INFORMATION The SN74CBT3253C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B on ports of the SN74CBT3253C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuringthattheswitchremainsintheproperOFFstate. The SN74CBT3253C is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE, 2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. WhenOE is low, the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing bidirectionaldataflowbetweenports.WhenOEishigh,theassociatedmultiplexer/demultiplexer is disabled, and ahigh-impedancestateexistsbetweentheAandBports. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for partial-power-down applications using I . The I feature ensures that damaging off off currentwillnotbackflowthroughthedevicewhenitispowereddown.Thedevicehasisolationduringpoweroff. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A QFN–RGY Reelof1000 SN74CBT3253CRGYR CU253C Tubeof40 SN74CBT3253CD SOIC–D CBT3253C Reelof2500 SN74CBT3253CDR Tubeof80 SN74CBT3253CDB –40(cid:176) Cto85(cid:176) C SSOP–DB CU253C Reelof2000 SN74CBT3253CDBR SSOP(QSOP)–DBQ Reelof2500 SN74CBT3253CDBQR CU253C Tubeof90 SN74CBT3253CPW TSSOP–PW CU253C Reelof2000 SN74CBT3253CPWR (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. FUNCTIONTABLE (eachmultiplexer/demultiplexer) INPUTS INPUT/OUTPUT FUNCTION OE S1 S0 A L L L B1 Aport=B1port L L H B2 Aport=B2port L H L B3 Aport=B3port L H H B4 Aport=B4port H X X X Disconnect 2 SubmitDocumentationFeedback

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 LOGICDIAGRAM(POSITIVELOGIC) 7 6 1A SW 1B1 5 SW 1B2 4 SW 1B3 3 SW 1B4 9 10 2A SW 2B1 11 SW 2B2 12 SW 2B3 13 SW 2B4 14 S0 2 S1 1 1OE 15 2OE SIMPLIFIEDSCHEMATIC,EACHFETSWITCH(SW) (1) EN (1) ENistheinternalenablesignalappliedtotheswitch. SubmitDocumentationFeedback 3

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC V Controlinputvoltagerange(2)(3) –0.5 7 V IN V SwitchI/Ovoltagerange(2)(3)(4) –0.5 7 V I/O I Controlinputclampcurrent V <0 –50 mA IK IN I I/Oportclampcurrent V <0 –50 mA I/OK I/O I ON-stateswitchcurrent(5) – 128 mA I/O ContinuouscurrentthroughV orGNDterminals – 100 mA CC Dpackage(6) 73 DBpackage(6) 82 q Packagethermalimpedance DBQpackage(6) 90 (cid:176) C/W JA PWpackage(6) 108 RGYpackage(7) 39 T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagesarewithrespecttogroundunlessotherwisespecified. (3) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputclamp-currentratingsareobserved. (4) V andV areusedtodenotespecificconditionsforV . I O I/O (5) I andI areusedtodenotespecificconditionsforI . I O I/O (6) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. (7) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-5. Recommended Operating Conditions(1) MIN MAX UNIT V Supplyvoltage 4 5.5 V CC V High-levelcontrolinputvoltage 2 5.5 V IH V Low-levelcontrolinputvoltage 0 0.8 V IL V Datainput/outputvoltage 0 5.5 V I/O T Operatingfree-airtemperature –40 85 (cid:176) C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 4 SubmitDocumentationFeedback

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 Electrical Characteristics(1) overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(2) MAX UNIT V Controlinputs V =4.5V, I =–18mA –1.8 V IK CC IN 0mA>I ‡ –50mA, V Datainputs V =5V, I SwitchOFF –2 V IKU CC V =V orGND, IN CC I Controlinputs V =5.5V, V =V orGND – 1 m A IN CC IN CC I (3) V =5.5V, VO=0to5.5V, SwitchOFF, – 10 m A OZ CC V =0, V =V orGND I IN CC I V =0, V =0to5.5V, V =0 10 m A off CC O I I V =5.5V, II/O=0, SwitchONorOFF 3 m A CC CC V =V orGND, IN CC D I (4) Controlinputs V =5.5V, Oneinputat3.4V, OtherinputsatV orGND 2.5 mA CC CC CC C Controlinputs V =3Vor0 3.5 pF in IN Aport 14 C V =3Vor0, SwitchOFF, V =V orGND pF io(OFF) I/O IN CC Bport 5.5 C V =3Vor0, SwitchON, V =V orGND 22 pF io(ON) I/O IN CC V =4V, CC V =2.4V, I =–15mA 8 12 TYPatV =4V I O CC ron(5) V =0 IO=64mA 3 6 W I V =4.5V I =30mA 3 6 CC O V =2.4V, I =–15mA 5 10 I O (1) V andI refertocontrolinputs.V,V ,I,andI refertodatapins. IN IN I O I O (2) AlltypicalvaluesareatV =5V(unlessotherwisenoted),T =25(cid:176) C. CC A (3) ForI/Oports,theparameterI includestheinputleakagecurrent. OZ (4) Thisistheincreaseinsupplycurrentforeachinputthatisatthespecifiedvoltagelevel,ratherthanV orGND CC (5) MeasuredbythevoltagedropbetweentheAandBterminalsattheindicatedcurrentthroughtheswitch.ON-stateresistanceis determinedbythelowerofthevoltagesofthetwo(AorB)terminals. Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =50pF(unlessotherwisenoted)(seeFigure3) L V =5V PARAMETER FROM TO VCC=4V –CC0.5V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX t (1) AorB BorA 0.24 0.15 ns pd t S A 5.9 1.5 5.4 ns pd(s) S B 6.2 1.5 5.8 t ns en OE AorB 5.7 1.5 5.3 S B 6.2 1.5 5.8 t ns dis OE AorB 5.7 1.5 5.3 (1) ThepropagationdelayisthecalculatedRCtimeconstantofthetypicalON-stateresistanceoftheswitchandthespecifiedload capacitance,whendrivenbyanidealvoltagesource(zerooutputimpedance). SubmitDocumentationFeedback 5

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 Undershoot Characteristics SeeFigure1andFigure2 PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT V V =5.5V, SwitchOFF, V =V orGND 2 V –0.3 V OUTU CC IN CC OH (1) AlltypicalvaluesareatV =5V(unlessotherwisenoted),T =25(cid:176) C. CC A 100 kΩ 50Ω 100 kΩ Figure1.DeviceTestSetup Figure2.TransientInputVoltage(V)and I OutputVoltage(V )Waveforms OUTU (SwitchOFF) 6 SubmitDocumentationFeedback

SN74CBT3253C DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS123B–JULY2003–REVISEDJANUARY2007 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω VG1 50 Ω TEST CIRCUIT DUT 7 V Input Generator S1 VI VO RL Open 50 Ω GND VG2 50 Ω CL RL (see Note A) TEST VCC S1 RL VI CL V∆ tpd(s) 5 V ± 0.5 V Open 500 Ω VCC or GND 50 pF 4 V Open 500 Ω VCC or GND 50 pF 5 V ± 0.5 V 7 V 500 Ω GND 50 pF 0.3 V tPLZ/tPZL 4 V 7 V 500 Ω GND 50 pF 0.3 V tPHZ/tPZH 5 V 4± V0.5 V OOppeenn 550000 ΩΩ VVCCCC 5500 ppFF 00..33 VV Output 3 V Control 1.5 V 1.5 V (VIN) 0 V tPZL tPLZ Output 3.5 V Output 3 V Waveform 1 1.5 V Control 1.5 V 1.5 V S1 at 7 V VOL + VD (VIN) 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − VD Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure3.TestCircuitandVoltageWaveforms SubmitDocumentationFeedback 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBT3253CD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253C & no Sb/Br) SN74CBT3253CDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU253C & no Sb/Br) SN74CBT3253CDBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU253C & no Sb/Br) SN74CBT3253CDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253C & no Sb/Br) SN74CBT3253CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253C & no Sb/Br) SN74CBT3253CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3253C & no Sb/Br) SN74CBT3253CPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU253C & no Sb/Br) SN74CBT3253CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU253C & no Sb/Br) SN74CBT3253CRGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU253C & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBT3253CDBQR SSOP DBQ 16 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBT3253CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74CBT3253CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBT3253CRGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT3253CDBQR SSOP DBQ 16 2500 340.5 338.1 20.6 SN74CBT3253CDR SOIC D 16 2500 333.2 345.9 28.6 SN74CBT3253CPWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74CBT3253CRGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 14X .0250 [0.635] 16 1 2X .189-.197 .175 [4.81-5.00] [4.45] NOTE 3 8 9 16X .008-.012 B .150-.157 [0.21-0.30] .069 MAX [3.81-3.98] [1.75] NOTE 4 .007 [0.17] C A B .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 0 - 8 [0.11-0.25] .016-.035 [0.41-0.88] DETAIL A (.041 ) TYPICAL [1.04] 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com

EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM SEE DETAILS 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 8 9 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL .002 MAX .002 MIN [0.05] [0.05] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 8 9 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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