SN74CBT3125 QUADRUPLE FET BUS SWITCH SCDS021I − MAY 1995 − REVISED SEPTEMBER 2002 (cid:2) Standard ’125-Type Pinout (D, DB, DGV, (cid:2) 5-Ω Switch Connection Between Two Ports and PW Packages) (cid:2) TTL-Compatible Input Levels D, DB, DGV, OR PW PACKAGE RGY PACKAGE DBQ PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) E C 1OE 1 14 VCC 1O VC NC 1 16 VCC 1A 2 13 4OE 1OE 2 15 4OE 1 14 1B 3 12 4A 1A 3 14 4A 1A 2 13 4OE 2OE 4 11 4B 1B 4 13 4B 1B 3 12 4A 2A 5 10 3OE 2OE 5 12 3OE 2OE 4 11 4B 2B 6 9 3A 2A 6 11 3A 2A 5 10 3OE GND 7 8 3B 2B 7 10 3B 2B 6 9 3A GND 8 9 NC 7 8 D B N 3 NC − No internal connection G description/ordering information The SN74CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74CBT3125RGYR CU125 Tube SN74CBT3125D SSOOIICC − DD CCBBTT33112255 Tape and reel SN74CBT3125DR −4400°CC ttoo 8855°CC SSOP − DB Tape and reel SN74CBT3125DBR CU125 SSOP (QSOP) − DBQ Tape and reel SN74CBT3125DBQR CU125 TSSOP − PW Tape and reel SN74CBT3125PWR CU125 TVSOP − DGV Tape and reel SN74CBT3125DGVR CU125 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each bus switch) INPUT FUNCTION OE L A port = B port H Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2002, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN74CBT3125 QUADRUPLE FET BUS SWITCH SCDS021I − MAY 1995 − REVISED SEPTEMBER 2002 logic diagram (positive logic) 2 3 1A 1B 1 1OE 5 6 2A 2B 4 2OE 9 8 3A 3B 10 3OE 12 11 4A 4B 13 4OE Pin numbers shown are for the D, DB, DGV, PW, and RGY packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 V VIL Low-level control input voltage 0.8 V TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBT3125 QUADRUPLE FET BUS SWITCH SCDS021I − MAY 1995 − REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 4 V, II = −18 mA −1.2 V II VCC = 5.5 V, VI = 5.5 V or GND ±1 μA ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 3 μA ΔICC‡ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Ci Control inputs VI = 3 V or 0 3 pF Cio(OFF) VO = 3 V or 0, OE = VCC 4 pF VTYCCP =a t4 V VC,C = 4 V VI = 2.4 V, II = 15 mA 16 22 rroonn§§ VVCCCC = 44..55 VV VVI = 00 IIII == 6340 mmAA 55 77 ΩΩ VI = 2.4 V, II = 15 mA 10 15 †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. §Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) PPAARRAAMMEETTEERR FROM TO VCC = 4 V VC±C0 .=5 5V V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd¶ A or B B or A 0.35 0.25 ns ten OE A or B 6 1.6 5.4 ns tdis OE A or B 5.1 1 4.7 ns ¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN74CBT3125 QUADRUPLE FET BUS SWITCH SCDS021I − MAY 1995 − REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 From Output 500 Ω S1 Open tpd Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V Output 1.5 V 1.5 V LOAD CIRCUIT Control 0 V tPZL tPLZ Output 3.5 V 3 V Waveform 1 Input 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − 0.3 V Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBT3125D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3125 & no Sb/Br) SN74CBT3125DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU125 & no Sb/Br) SN74CBT3125DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3125 & no Sb/Br) SN74CBT3125DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3125 & no Sb/Br) SN74CBT3125PW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125PWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CU125 & no Sb/Br) SN74CBT3125RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CU125 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBT3125DBQR SSOP DBQ 16 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBT3125DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBT3125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBT3125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBT3125RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT3125DBQR SSOP DBQ 16 2500 340.5 338.1 20.6 SN74CBT3125DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74CBT3125DR SOIC D 14 2500 367.0 367.0 38.0 SN74CBT3125PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74CBT3125RGYR VQFN RGY 14 3000 367.0 367.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 14X .0250 [0.635] 16 1 2X .189-.197 .175 [4.81-5.00] [4.45] NOTE 3 8 9 16X .008-.012 B .150-.157 [0.21-0.30] .069 MAX [3.81-3.98] [1.75] NOTE 4 .007 [0.17] C A B .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 0 - 8 [0.11-0.25] .016-.035 [0.41-0.88] DETAIL A (.041 ) TYPICAL [1.04] 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com

EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM SEE DETAILS 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 8 9 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL .002 MAX .002 MIN [0.05] [0.05] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 8 9 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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