ICGOO在线商城 > 集成电路(IC) > 逻辑 - 信号开关,多路复用器,解码器 > SN74CBT1G125DCKR
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SN74CBT1G125DCKR产品简介:
ICGOO电子元器件商城为您提供SN74CBT1G125DCKR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74CBT1G125DCKR价格参考¥0.60-¥1.16。Texas InstrumentsSN74CBT1G125DCKR封装/规格:逻辑 - 信号开关,多路复用器,解码器, Bus Switch 1 x 1:1 SC-70-5。您可以下载SN74CBT1G125DCKR参考资料、Datasheet数据手册功能说明书,资料中有SN74CBT1G125DCKR 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC SING FET BUS SW SC70-5数字总线开关 IC Single FET |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 开关 IC,数字总线开关 IC,Texas Instruments SN74CBT1G125DCKR74CBT |
数据手册 | |
产品型号 | SN74CBT1G125DCKR |
产品目录页面 | |
产品种类 | 数字总线开关 IC |
传播延迟时间 | 0.25 ns |
供应商器件封装 | SC-70-5 |
其它名称 | 296-6410-6 |
包装 | Digi-Reel® |
单位重量 | 2.500 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
导通电阻—最大值 | 20 Ohms |
封装 | Reel |
封装/外壳 | 6-TSSOP(5 引线),SC-88A,SOT-353 |
封装/箱体 | SC-70-5 |
工作温度 | -40°C ~ 85°C |
工厂包装数量 | 3000 |
开关数量 | 1 |
技术 | CBT |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
标准包装 | 1 |
独立电路 | 1 |
电压-电源 | 4.5 V ~ 5.5 V |
电压源 | 单电源 |
电流-输出高,低 | - |
电源电压-最大 | 5.5 V |
电源电压-最小 | 4 V |
电源电流 | 1 uA |
电路 | 1 x 1:1 |
类型 | FET 总线开关 |
系列 | SN74CBT1G125 |
逻辑系列 | CBT |
SN74CBT1G125 SINGLE FET BUS SWITCH SCDS046G – FEBRUARY 1998 – REVISED JANUARY 2003 (cid:0) 5-Ω Switch Connection Between Two Ports DBV OR DCK PACKAGE (cid:0) (TOP VIEW) TTL-Compatible Control Input Levels (cid:0) Latch-Up Performance Exceeds 250 mA Per OE 1 5 VCC JESD 17 A 2 (cid:0) ESD Protection Exceeds JESD 22 GND 3 4 B – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) description/ordering information The SN74CBT1G125 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING‡ Reel of 3000 SN74CBT1G125DBVR SSOOTT ((SSOOTT-2233)) – DDBBVV SS2255_ Reel of 250 SN74CBT1G125DBVT –4400°°CC ttoo 8855°°CC Reel of 3000 SN74CBT1G125DCKR SSOOTT ((SSCC--7700)) –– DDCCKK SSMM_ Reel of 250 SN74CBT1G125DCKT †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUT FUNCTION OE L A port = B port H Disconnect logic diagram (positive logic) 2 4 A B 1 OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
SN74CBT1G125 SINGLE FET BUS SWITCH SCDS046G – FEBRUARY 1998 – REVISED JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W JA DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 V VIL Low-level control input voltage 0.8 V TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 V II VCC = 5.5 V, VI = 5.5 V or GND ±1 µA ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 1 µA Ci Control input VI = 3 V or 0 3 pF Cio(OFF) VO = 3 V or 0, OE = VCC 4 pF VCC = 4 V, TYP at VCC = 4 V, VI = 2.4 V, II = 15 mA 14 20 rron§§§ VVII == 00 II = 64 mA 5 7 ΩΩ VCC = 4.5 V II = 30 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 ‡All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. §Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) VCC = 5 V PARAMETER FROM TO VCC = 4 V ± 0.5 V UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd¶ A or B B or A 0.35 0.25 ns ten OE A or B 5.5 1.6 4.9 ns tdis OE A or B 4.5 1 4.2 ns ¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT1G125 SINGLE FET BUS SWITCH SCDS046G – FEBRUARY 1998 – REVISED JANUARY 2003 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 From Output 500 Ω S1 Open tpd Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V Output 1.5 V 1.5 V LOAD CIRCUIT Control 0 V tPZL tPLZ Output 3.5 V 3 V Waveform 1 Input 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH – 0.3 V Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 74CBT1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 (S25G, S25J, S25S) & no Sb/Br) 74CBT1G125DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (SM3, SMS, SMT, SM & no Sb/Br) U) SN74CBT1G125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (S25G, S25J, S25S) & no Sb/Br) SN74CBT1G125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (S25J, S25S) & no Sb/Br) SN74CBT1G125DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (SM3, SMS, SMT, SM & no Sb/Br) U) SN74CBT1G125DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (SM3, SMS) & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2020 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBT1G125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74CBT1G125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74CBT1G125DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74CBT1G125DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74CBT1G125DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74CBT1G125DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74CBT1G125DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74CBT1G125DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74CBT1G125DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 SN74CBT1G125DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74CBT1G125DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT1G125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74CBT1G125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74CBT1G125DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74CBT1G125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74CBT1G125DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74CBT1G125DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74CBT1G125DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74CBT1G125DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74CBT1G125DCKR SC70 DCK 5 3000 203.0 203.0 35.0 SN74CBT1G125DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74CBT1G125DCKT SC70 DCK 5 250 202.0 201.0 28.0 PackMaterials-Page2
PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com
EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com
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