(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 (cid:1) Member of the Texas Instruments DGG OR DL PACKAGE Widebus Family (TOP VIEW) (cid:1) Undershoot Protection for Off-Isolation on S0 1 56 S1 A and B Ports Up To −2 V 1A 2 55 S2 (cid:1) Bidirectional Data Flow, With Near-Zero 1B3 3 54 1B1 Propagation Delay 2A 4 53 1B2 (cid:1) Low ON-State Resistance (ron) 2B3 5 52 2B1 Characteristics (ron = 3 Ω Typical) 3A 6 51 2B2 (cid:1) Low Input/Output Capacitance Minimizes 3B3 7 50 3B1 Loading and Signal Distortion GND 8 49 GND (Cio(OFF) = 5.5 pF Typical) 4A 9 48 3B2 (cid:1) Data and Control Inputs Provide 4B3 10 47 4B1 Undershoot Clamp Diodes 5A 11 46 4B2 (cid:1) 5B3 12 45 5B1 Low Power Consumption (I = 3 µA Max) 6A 13 44 5B2 CC (cid:1) 6B3 14 43 6B1 V Operating Range From 4 V to 5.5 V CC 7A 15 42 6B2 (cid:1) Data I/Os Support 0 to 5-V Signaling Levels 7B3 16 41 7B1 (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) VCC 17 40 7B2 (cid:1) Control Inputs Can Be Driven by TTL or 8A 18 39 8B1 5-V/3.3-V CMOS Outputs GND 19 38 GND (cid:1) I Supports Partial-Power-Down Mode 8B3 20 37 8B2 off Operation 9A 21 36 9B1 (cid:1) 9B3 22 35 9B2 Latch-Up Performance Exceeds 100 mA Per 10A 23 34 10B1 JESD 78, Class II (cid:1) 10B3 24 33 10B2 ESD Performance Tested Per JESD 22 11A 25 32 11B1 − 2000-V Human-Body Model 11B3 26 31 11B2 (A114-B, Class II) 12A 27 30 12B1 − 1000-V Charged-Device Model (C101) 12B3 28 29 12B2 (cid:1) Supports Both Digital and Analog Applications: PCI Interface, Bus Isolation, Low-Distortion Signal Gating description/ordering information ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CBT16214CDL SSSSOOPP −− DDLL CCBBTT1166221144CC Tape and reel SN74CBT16214CDLR −−4400°°CC ttoo 8855°°CC Tube SN74CBT16214CDGG TTSSSSOOPP −− DDGGGG CCBBTT1166221144CC Tape and reel SN74CBT16214CDGGR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:20)(cid:22)(cid:13)(cid:24)(cid:18)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) (cid:24)(cid:30)(cid:7)(cid:30) (cid:31)!"#$%&’(cid:31)#! (cid:31)( )*$$+!’ &( #" ,*-.(cid:31))&’(cid:31)#! /&’+0 Copyright  2003, Texas Instruments Incorporated (cid:20)$#/*)’( )#!"#$% ’# (,+)(cid:31)"(cid:31))&’(cid:31)#!( ,+$ ’1+ ’+$%( #" (cid:7)+2&( (cid:12)!(’$*%+!’( (’&!/&$/ 3&$$&!’40 (cid:20)$#/*)’(cid:31)#! ,$#)+(((cid:31)!5 /#+( !#’ !+)+((&$(cid:31).4 (cid:31)!).*/+ ’+(’(cid:31)!5 #" &.. ,&$&%+’+$(0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 description/ordering information (continued) The SN74CBT16214C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and on B ports of the SN74CBT16214C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT16214C is a 12-bit 1-of-3 multiplexer/demultiplexer. The select (S0, S1, S2) inputs control the data path of each multiplexer/demultiplexer. When the multiplexer/demultiplexer is enabled, the A port is connected to the B port, allowing bidirectional data flow between ports. When the multiplexer/demultiplexer is disabled, a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using I . The I feature ensures that off off damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, each select input should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. FUNCTION TABLE INPUTS IINNPPUUTT//OOUUTTPPUUTT FFUUNNCCTTIIOONN S2 S1 S0 A L L L Z Disconnect L L H B1 A port = B1 port L H L B2 A port = B2 port L H H Z Disconnect H L L Z Disconnect H L H B3 A port = B3 port H H L B1 A port = B1 port H H H B2 A port = B2 port 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 logic diagram (positive logic) 2 54 1A SW 1B1 53 SW 1B2 3 SW 1B3 27 30 12A SW 12B1 29 SW 12B2 28 SW 12B3 1 S0 56 S1 55 S2 simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† †EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V IN Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I/O Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA I/O Continuous current through V or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W JA DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 5.5 V VIL Low-level control input voltage 0 0.8 V VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Control inputs VCC = 4.5 V, IIN = −18 mA −1.8 V 0 mA > II ≥ −50 mA, VIKU Data inputs VCC = 5 V, VIN = VCC or GND, Switch OFF −2 V IIN Control inputs VCC = 5.5 V, VIN = VCC or GND ±1 µA IOZ‡ VCC = 5.5 V, VVIO = = 0 0, to 5.5 V, SVIwNit c=h V OCFCF ,or GND ±10 µA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA ICC VCC = 5.5 V, IVI/ION == 0V,CC or GND, Switch ON or OFF 3 µA ∆ICC§ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Cin Control inputs VIN = 3 V or 0 3.5 pF A port 10 pF CCiioo((OOFFFF)) VVII//OO == 33 VV oorr 00,, SSwwiittcchh OOFFFF,, VVIINN == VVCCCC oorr GGNNDD B port 5.5 pF Cio(ON) VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 18 pF VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, IO = −15 mA 8 12 rroonn¶¶ IO = 64 mA 3 6 ΩΩ VVII == 00 VVCCCC == 44..55 VV IO = 30 mA 3 6 VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡For I/O ports, the parameter IOZ includes the input leakage current. §This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 3) VCC = 5 V PPAARRAAMMEETTEERR FROM TO VCC = 4 V ± 0.5 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd# A or B B or A 0.24 0.15 ns tpd(s) S A 6.7 1.5 6.3 ns ten S B 7.2 1.5 6.6 ns tdis S B 7.5 1.5 7.3 ns #The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOUTU VCC = 5.5 V, Switch OFF, VIN = VCC or GND 2 VOH−0.3 V †All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC 11 V 5.5 V Input 100 kΩ Input 90 % 90 % Generator 50 Ω (Open 2 ns 2 ns DUT Socket) Ax Bx 10 % 10 % −2 V 100 kΩ 10 pF 20 ns VS Output VOH (VOUTU) VOH − 0.3 Figure 1. Device Test Setup Figure 2. Transient Input Voltage (V) and Output I Voltage (V ) Waveforms OUTU (Switch OFF) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:4)(cid:5) (cid:8)(cid:10)(cid:11)(cid:6)(cid:12)(cid:7) (cid:8)(cid:11)(cid:13)(cid:14)(cid:11)(cid:15) (cid:14)(cid:16)(cid:7) (cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22)(cid:23)(cid:24)(cid:16)(cid:17)(cid:18)(cid:19)(cid:7)(cid:12)(cid:20)(cid:19)(cid:16)(cid:21)(cid:16)(cid:22) (cid:25)(cid:11)(cid:26) (cid:6)(cid:18)(cid:1) (cid:1)(cid:27)(cid:12)(cid:7)(cid:5)(cid:28) (cid:27)(cid:12)(cid:7)(cid:28) (cid:29)(cid:10)(cid:11)(cid:26) (cid:18)(cid:2)(cid:24)(cid:16)(cid:22)(cid:1)(cid:28)(cid:13)(cid:13)(cid:7) (cid:20)(cid:22)(cid:13)(cid:7)(cid:16)(cid:5)(cid:7)(cid:12)(cid:13)(cid:2) SCDS121B − JUNE 2003 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω VG1 50 Ω TEST CIRCUIT DUT 7 V Input Generator S1 VI VO RL Open 50 Ω GND VG2 50 Ω CL RL (see Note A) TEST VCC S1 RL VI CL V∆ tpd(s) 5 V ±0.5 V Open 500 Ω VCC or GND 50 pF 4 V Open 500 Ω VCC or GND 50 pF 5 V ±0.5 V 7 V 500 Ω GND 50 pF 0.3 V tPLZ/tPZL 4 V 7 V 500 Ω GND 50 pF 0.3 V tPHZ/tPZH 5 V ±0.5 V Open 500 Ω VCC 50 pF 0.3 V 4 V Open 500 Ω VCC 50 pF 0.3 V Output 3 V Control 1.5 V 1.5 V (VIN) 0 V tPZL tPLZ Output 3.5 V Output 3 V Waveform 1 1.5 V Control 1.5 V 1.5 V S1 at 7 V VOL + V∆ (VIN) 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − V∆ Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 74CBT16214CDGGRE4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74CBT16214CDGGRG4 ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBT16214CDGGR ACTIVE TSSOP DGG 56 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBT16214CDL ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBT16214CDLG4 ACTIVE SSOP DL 56 20 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBT16214CDLR ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) SN74CBT16214CDLRG4 ACTIVE SSOP DL 56 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) SN74CBT16214CDGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74CBT16214CDLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT16214CDGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74CBT16214CDLR SSOP DL 56 1000 346.0 346.0 49.0 PackMaterials-Page2

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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