(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:8)(cid:11) (cid:10)(cid:4)(cid:12)(cid:6)(cid:13)(cid:7) (cid:14)(cid:15)(cid:7) (cid:6)(cid:16)(cid:1) (cid:1)(cid:17)(cid:13)(cid:7)(cid:5)(cid:18) SCDS028M − JULY 1995 − REVISED SEPTEMBER 2003 (cid:1) Member of the Texas Instruments DGG, DGV, OR DL PACKAGE Widebus Family (TOP VIEW) (cid:1) 5-Ω Switch Connection Between Two Ports (cid:1) NC 1 56 1OE TTL-Compatible Input Levels 1A1 2 55 2OE 1A2 3 54 1B1 description/ordering information 1A3 4 53 1B2 The SN74CBT16211A provides 24 bits of 1A4 5 52 1B3 high-speed TTL-compatible bus switching. The 1A5 6 51 1B4 low on-state resistance of the switch allows 1A6 7 50 1B5 connections to be made with minimal propagation GND 8 49 GND delay. 1A7 9 48 1B6 1A8 10 47 1B7 The device operates as a dual 12-bit bus switch or 1A9 11 46 1B8 single 24-bit bus switch. When 1OE is low, 1A is 1A10 12 45 1B9 connected to 1B. When 2OE is low, 2A is 1A11 13 44 1B10 connected to 2B. 1A12 14 43 1B11 2A1 15 42 1B12 2A2 16 41 2B1 V 17 40 2B2 CC 2A3 18 39 2B3 GND 19 38 GND 2A4 20 37 2B4 2A5 21 36 2B5 2A6 22 35 2B6 2A7 23 34 2B7 2A8 24 33 2B8 2A9 25 32 2B9 2A10 26 31 2B10 2A11 27 30 2B11 2A12 28 29 2B12 NC − No internal connection ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CBT16211ADL SSSSOOPP −− DDLL CCBBTT1166221111AA Tape and reel SN74CBT16211ADLR TSSOP − DGG Tape and reel SN74CBT16211ADGGR CBT16211A −−4400°°CC ttoo 8855°°CC TVSOP − DGV Tape and reel SN74CBT16211ADGVR CY211A VFBGA − GQL SN74CBT16211AGQLR TTaappee aanndd rreeeell CCYY221111AA VFBGA − ZQL (Pb-free) SN74CBT16211AZQLR †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. (cid:19)(cid:20)(cid:21)(cid:22)(cid:16)(cid:5)(cid:7)(cid:13)(cid:21)(cid:2) (cid:22)(cid:11)(cid:7)(cid:11) (cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) (cid:23)(cid:31) !"(cid:27)(cid:27)#(cid:24)(cid:30) (cid:29)(cid:31) (cid:26)(cid:25) $"%&(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24) ’(cid:29)(cid:30)#( Copyright  2003, Texas Instruments Incorporated (cid:19)(cid:27)(cid:26)’"!(cid:30)(cid:31) !(cid:26)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28) (cid:30)(cid:26) (cid:31)$#!(cid:23)(cid:25)(cid:23)!(cid:29)(cid:30)(cid:23)(cid:26)(cid:24)(cid:31) $#(cid:27) (cid:30))# (cid:30)#(cid:27)(cid:28)(cid:31) (cid:26)(cid:25) (cid:7)#*(cid:29)(cid:31) (cid:13)(cid:24)(cid:31)(cid:30)(cid:27)"(cid:28)#(cid:24)(cid:30)(cid:31) (cid:31)(cid:30)(cid:29)(cid:24)’(cid:29)(cid:27)’ +(cid:29)(cid:27)(cid:27)(cid:29)(cid:24)(cid:30),( (cid:19)(cid:27)(cid:26)’"!(cid:30)(cid:23)(cid:26)(cid:24) $(cid:27)(cid:26)!#(cid:31)(cid:31)(cid:23)(cid:24)- ’(cid:26)#(cid:31) (cid:24)(cid:26)(cid:30) (cid:24)#!#(cid:31)(cid:31)(cid:29)(cid:27)(cid:23)&, (cid:23)(cid:24)!&"’# (cid:30)#(cid:31)(cid:30)(cid:23)(cid:24)- (cid:26)(cid:25) (cid:29)&& $(cid:29)(cid:27)(cid:29)(cid:28)#(cid:30)#(cid:27)(cid:31)( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:8)(cid:11) (cid:10)(cid:4)(cid:12)(cid:6)(cid:13)(cid:7) (cid:14)(cid:15)(cid:7) (cid:6)(cid:16)(cid:1) (cid:1)(cid:17)(cid:13)(cid:7)(cid:5)(cid:18) SCDS028M − JULY 1995 − REVISED SEPTEMBER 2003 GQL OR ZQL PACKAGE (TOP VIEW) terminal assignments 1 2 3 4 5 6 1 2 3 4 5 6 A A 1A2 1A1 NC 1OE 2OE 1B1 B B 1A5 1A4 1A3 1B2 1B3 1B4 C C 1A7 GND 1A6 1B5 GND 1B6 D 1A10 1A8 1A9 1B8 1B7 1B9 D E 1A12 1A11 1B10 1B11 E F 2A1 2A2 2B1 1B12 F G VCC GND 2A3 2B3 GND 2B2 G H 2A4 2A5 2A6 2B6 2B5 2B4 H J 2A7 2A8 2A9 2B9 2B8 2B7 J K 2A10 2A11 2A12 2B12 2B11 2B10 K NC − No internal connection FUNCTION TABLE (each 12-bit bus switch) INPUTS INPUTS/OUTPUTS 1OE 2OE 1A, 1B 2A, 2B L L 1A = 1B 2A = 2B L H 1A = 1B Z H L Z 2A = 2B H H Z Z logic diagram (positive logic) 2 54 1A1 1B1 14 42 1A12 1B12 56 1OE 15 41 2A1 2B1 28 29 2A12 2B12 55 2OE Pin numbers shown are for the DGG, DGV, and DL packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:8)(cid:11) (cid:10)(cid:4)(cid:12)(cid:6)(cid:13)(cid:7) (cid:14)(cid:15)(cid:7) (cid:6)(cid:16)(cid:1) (cid:1)(cid:17)(cid:13)(cid:7)(cid:5)(cid:18) SCDS028M − JULY 1995 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 V VIL Low-level control input voltage 0.8 V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT VIK VCC = 4.5 V, II = −18 mA −1.2 V VCC = 0 V, VI = 5.5 V 10 IIII VCC = 5.5 V, VI = 5.5 V or GND ±1 µAA ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA ∆ICC§ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Ci Control inputs VI = 3 V or 0 3 pF Cio(off) VO = 3 V or 0, OE = VCC 5.5 pF VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, II = 15 mA 14 20 rroonn¶¶ VVII == 00 II = 64 mA 5 7 ΩΩ VVCCCC == 44..55 VV II = 30 mA 5 7 VI = 2.4 V, II = 15 mA 8 12 ‡All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. §This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:8)(cid:11) (cid:10)(cid:4)(cid:12)(cid:6)(cid:13)(cid:7) (cid:14)(cid:15)(cid:7) (cid:6)(cid:16)(cid:1) (cid:1)(cid:17)(cid:13)(cid:7)(cid:5)(cid:18) SCDS028M − JULY 1995 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) VCC = 5 V PPAARRAAMMEETTEERR FROM TO VCC = 4 V ± 0.5 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd† A or B B or A 0.35 0.25 ns ten OE A or B 9.3 3.3 8.6 ns tdis OE A or B 7.1 2.8 7.9 ns †The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 From Output 500 Ω S1 Open tpd Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V Output 1.5 V 1.5 V LOAD CIRCUIT Control 0 V tPZL tPLZ Output 3.5 V 3 V Waveform 1 1.5 V Input 1.5 V 1.5 V S1 at 7 V VOL + 0.3 V 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 1.5 V VOH − 0.3 V Output 1.5 V 1.5 V S1 at Open VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74CBT16211ADGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211A & no Sb/Br) SN74CBT16211ADGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211A & no Sb/Br) SN74CBT16211ADGVR ACTIVE TVSOP DGV 56 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CY211A & no Sb/Br) SN74CBT16211ADL ACTIVE SSOP DL 56 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211A & no Sb/Br) SN74CBT16211ADLG4 ACTIVE SSOP DL 56 20 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211A & no Sb/Br) SN74CBT16211ADLR ACTIVE SSOP DL 56 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 22-Jan-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBT16211ADGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74CBT16211ADGVR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1 SN74CBT16211ADLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Jan-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBT16211ADGGR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74CBT16211ADGVR TVSOP DGV 56 2000 367.0 367.0 45.0 SN74CBT16211ADLR SSOP DL 56 1000 367.0 367.0 55.0 PackMaterials-Page2

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 SEATING PLANE TYP 7.9 A PIN 1 ID 0.1 C AREA 54X 0.5 56 1 14.1 2X 13.9 13.5 NOTE 3 28 29 0.27 B 6.2 56X 0.17 1.2 MAX 6.0 0.08 C A B (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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