(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 (cid:1) (cid:1) Output Voltage Translation Tracks V V Operating Range From 2.3 V to 3.6 V CC CC (cid:1) (cid:1) Supports Mixed-Mode Signal Operation On Data I/Os Support 0- to 5-V Signaling All Data I/O Ports Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, − 5-V Input Down To 3.3-V Output Level 5 V) Shift With 3.3-V VCC (cid:1) Control Inputs Can Be Driven by TTL or − 5-V/3.3-V Input Down To 2.5-V Output 5-V/3.3-V CMOS Outputs Level Shift With 2.5-V VCC (cid:1) I Supports Partial-Power-Down Mode (cid:1) off 5-V-Tolerant I/Os With Device Powered Up Operation or Powered Down (cid:1) Latch-Up Performance Exceeds 250 mA Per (cid:1) Bidirectional Data Flow, With Near-Zero JESD 17 Propagation Delay (cid:1) ESD Performance Tested Per JESD 22 (cid:1) Low ON-State Resistance (r ) on − 2000-V Human-Body Model Characteristics (r = 5 Ω Typical) on (A114-B, Class II) (cid:1) Low Input/Output Capacitance Minimizes − 1000-V Charged-Device Model (C101) Loading (C = 8 pF Typical) (cid:1) io(OFF) Supports Digital Applications: Level (cid:1) Data and Control Inputs Provide Translation, Memory Interleaving, Bus Undershoot Clamp Diodes Isolation (cid:1) (cid:1) Low Power Consumption Ideal for Low-Power Portable Equipment (I = 20 µA Max) CC DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) BE 1 24 V CC 1B1 2 23 5B2 1A1 3 22 5A2 1A2 4 21 5A1 1B2 5 20 5B1 2B1 6 19 4B2 2A1 7 18 4A2 2A2 8 17 4A1 2B2 9 16 4B1 3B1 10 15 3B2 3A1 11 14 3A2 GND 12 13 BX description/ordering information ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN74CB3T3383DW SSOOIICC −− DDWW CCBB33TT33338833 Tape and reel SN74CB3T3383DWR SSOP (QSOP) − DBQ Tape and reel SN74CB3T3383DBQR CB3T3383 −−4400°°CC ttoo 8855°°CC Tube SN74CB3T3383PW TTSSSSOOPP −− PPWW KKSS338833 Tape and reel SN74CB3T3383PWR TVSOP − DGV Tape and reel SN74CB3T3383DGVR KS383 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:30)(cid:29)(cid:28)(cid:31)(cid:16)(cid:5)(cid:8)(cid:13)(cid:28)(cid:2) (cid:31)(cid:19)(cid:8)(cid:19) !"#$%&’(!$" !) *+%%,"( ’) $# -+./!*’(!$" 0’(,(cid:23) Copyright  2004, Texas Instruments Incorporated (cid:30)%$0+*() *$"#$%& ($ )-,*!#!*’(!$") -,% (1, (,%&) $# (cid:8),2’) (cid:13)")(%+&,"() )(’"0’%0 3’%%’"(4(cid:23) (cid:30)%$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))’%!/4 !"*/+0, (,)(!"5 $# ’// -’%’&,(,%)(cid:23) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 description/ordering information (continued) The SN74CB3T3383 is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance (r ), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data on I/O ports by providing voltage translation that tracks V . The SN74CB3T3383 supports systems using 5-V CC TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). VCC 5.5 V VCC IN OUT ≈VCC ≈VCC − 1 V CB3T ≈VCC − 1 V 0 V 0 V Input Voltages Output Voltages NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, then the output high voltage (VOH) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC Voltage Translation Characteristics The SN74CB3T3383 is organized as a 10-bit bus switch or as a 5-bit bus-exchange with enable (BE) input. When used as a 5-bit bus-exchange, the device provides data exchanging between four signal ports. When BE is low, the bus-exchange switch is ON, and the select input (BX) controls the data path. When BE is high, the bus-exchange switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using I . The I feature ensures that off off damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, BE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 FUNCTION TABLE (each 5-bit switch) INPUTS INPUTS/OUTPUTS FFUUNNCCTTIIOONN BE BX A1 A2 A1 port = B1 port L L B1 B2 A2 port = B2 port A1 port = B2 port L H B2 B1 A2 port = B1 port H X Z Z Disconnect logic diagram (positive logic) 3 2 1A1 SW 1B1 SW SW 4 5 1A2 SW 1B2 21 20 5A1 SW 5B1 SW SW 22 23 5A2 SW 5B2 1 BE 13 BX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 simplified schematic, each FET switch (SW) A B VG† Control Circuit EN‡ †Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. ‡EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§ Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V IN Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I/O Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA I/O Continuous current through V or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θJA (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg §Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VCC = 2.3 V to 2.7 V 1.7 5.5 VVIIHH HHiigghh--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VVIILL LLooww--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 0 0.8 VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VCC = 3 V, VIK II = −18 mA −1.2 V VOH See Figures 3 and 4 IIN‡ Control inputs VVCINC‡ == 33..66 VV, to 5.5 V or GND ±10 µA VVCCCC == 33..66 VV,, VI = VCC − 0.7 V to 5.5 V ±20 IIII SSwwiittcchh OONN,, VI = 0.7 V to VCC − 0.7 V −40 µµAA VVIN == VVCC oorr GGNNDD VI = 0 to 0.7 V ±5 VCC = 3.6 V, VO = 0 to 5.5 V, IOZ§ VI = 0, ±10 µA Switch OFF, VIN = VCC or GND VCC = 0, Ioff VO = 0 to 5.5 V, 10 µA VI = 0, VCC = 3.6 V, VI = VCC or GND 20 IICCCC IISII//wOOi t==ch 00 O,, N or OFF, µAA VIN = VCC or GND VI = 5.5 V 20 VCC = 3 V to 3.6 V, ∆ICC¶ Control inputs One input at VCC − 0.6 V, 300 µA Other inputs at VCC or GND VCC = 3.3 V, Cin Control inputs VIN = VCC or GND 4 pF VCC = 3.3 V, Cio(OFF) VI/O = 5.5 V, 3.3 V, or GND, 8 pF Switch OFF, VIN = VCC or GND VCCCC = 3.3 V, VI/O = 5.5 V or 3.3 V 7 CCiioo((OONN)) SSwwiittcchh OONN,, ppFF VIN = VCC or GND VI/O = GND 21 VCCCC = 2.3 V, IO = 24 mA 5 9 TTYYPP aatt VVCCCC == 22..55 VV,, rroonn## VI = 0 IO = 16 mA 5 9 ΩΩ VVCCCC == 33 VV,, IO = 64 mA 5 8 VI = 0 IO = 32 mA 5 8 †All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. §For I/O ports, the parameter IOZ includes the input leakage current. ¶This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. #Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR FROM TO ± 0.2 V ± 0.3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX tpd† A or B B or A 0.15 0.25 nnss tpd(s) BX A or B 1 15 1 10 ten BE A or B 1 13.5 1 9 ns tdis BE A or B 1 7 1 8.5 ns †The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω VG1 50 Ω TEST CIRCUIT DUT 2 × VCC Input Generator S1 VI VO RL Open 50 Ω GND VG2 50 Ω CL RL (see Note A) TEST VCC S1 RL VI CL V∆ tpd(s) 2.5 V ±0.2 V Open 500 Ω 3.6 V or GND 30 pF 3.3 V ±0.3 V Open 500 Ω 5.5 V or GND 50 pF tPLZ/tPZL 2.5 V ±0.2 V 2 × VCC 500 Ω GND 30 pF 0.15 V 3.3 V ±0.3 V 2 × VCC 500 Ω GND 50 pF 0.3 V 2.5 V ±0.2 V Open 500 Ω 3.6 V 30 pF 0.15 V tPHZ/tPZH 3.3 V ±0.3 V Open 500 Ω 5.5 V 50 pF 0.3 V Output VCC Control VCC/2 VCC/2 (VIN) 0 V tPZL tPLZ Output VCC Output VCC Waveform 1 Control VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + V∆ (VIN) 0 V (see Note B) VOL tPZH tPHZ tPLH tPHL Output VOH VOH Waveform 2 VOH − V∆ Output VCC/2 VCC/2 S1 at Open VCC/2 VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 2. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs INPUT VOLTAGE INPUT VOLTAGE 4.0 4.0 VCC = 2.3 V VCC = 3 V IO = 1 µA IO = 1 µA TA = 25°C TA = 25°C V 3.0 V 3.0 − − e e g g a a olt olt V 2.0 V 2.0 ut ut p p ut ut O O − 1.0 − 1.0 V O V O 0.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VI − Input Voltage − V VI − Input Voltage − V Figure 3. Data Output Voltage vs Data Input Voltage 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:7)(cid:7)(cid:9)(cid:7) (cid:10)(cid:11)(cid:12)(cid:6)(cid:13)(cid:8) (cid:14)(cid:15)(cid:8) (cid:6)(cid:16)(cid:1)(cid:12)(cid:15)(cid:17)(cid:5)(cid:18)(cid:19)(cid:2)(cid:20)(cid:15) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:22)(cid:23)(cid:24)(cid:12)(cid:25)(cid:26)(cid:7)(cid:23)(cid:7)(cid:12)(cid:25) (cid:27)(cid:28)(cid:21)(cid:12)(cid:25)(cid:28)(cid:27)(cid:8)(cid:19)(cid:20)(cid:15) (cid:6)(cid:16)(cid:1) (cid:1)(cid:21)(cid:13)(cid:8)(cid:5)(cid:18) (cid:21)(cid:13)(cid:8)(cid:18) (cid:24)(cid:12)(cid:25)(cid:12)(cid:8)(cid:28)(cid:27)(cid:15)(cid:29)(cid:19)(cid:2)(cid:8) (cid:27)(cid:15)(cid:25)(cid:15)(cid:27) (cid:1)(cid:18)(cid:13)(cid:14)(cid:8)(cid:15)(cid:29) SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE HIGH OUTPUT VOLTAGE HIGH vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 4.0 4.0 Output Voltage High − V 233...505 VVTACI = C= 5 =8.55 2 °V.C3 V to 3.6 V 1182604 m 0 mm AµAAA Output Voltage High − V 233...505 VVTACI = C= 5 =2.55 2 °V.C3 V to 3.6 V 1182604 m 0 mm AµAAA V − OH 2.0 V − OH 2.0 1.5 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V VCC − Supply Voltage − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4.0 VCC = 2.3 V to 3.6 V V VI = 5.5 V 100 µA h − 3.5 TA = –40°C 8 mA Hig 1264 mmAA e 3.0 g a olt V ut 2.5 p ut O − 2.0 V OH 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V Figure 4. VOH Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CB3T3383DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS383 & no Sb/Br) SN74CB3T3383DWR ACTIVE SOIC DW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T3383 & no Sb/Br) SN74CB3T3383PW ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS383 & no Sb/Br) SN74CB3T3383PWR ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS383 & no Sb/Br) SN74CB3T3383PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS383 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CB3T3383DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CB3T3383DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74CB3T3383PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CB3T3383DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74CB3T3383DWR SOIC DW 24 2000 350.0 350.0 43.0 SN74CB3T3383PWR TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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