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SN74AUP1G98DCKR产品简介:

ICGOO电子元器件商城为您提供SN74AUP1G98DCKR由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 SN74AUP1G98DCKR价格参考¥0.80-¥2.31。Texas InstrumentsSN74AUP1G98DCKR封装/规格:逻辑 - 栅极和逆变器 - 多功能,可配置, Configurable Multiple Function Configurable 1 Circuit 3 Input SC-70-6。您可以下载SN74AUP1G98DCKR参考资料、Datasheet数据手册功能说明书,资料中有SN74AUP1G98DCKR 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC CONFIG MULT-FUNC GATE SC70-6逻辑门 Lo-Pwr Conf Mult Function Gate

产品分类

逻辑 - 栅极和逆变器 - 多功能,可配置

品牌

Texas Instruments

产品手册

点击此处下载产品Datasheet

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

逻辑集成电路,逻辑门,Texas Instruments SN74AUP1G98DCKR74AUP

数据手册

点击此处下载产品Datasheet

产品型号

SN74AUP1G98DCKR

PCN设计/规格

点击此处下载产品Datasheet

产品

MUX Gates

产品种类

逻辑门

传播延迟时间

21.6 ns

低电平输出电流

4 mA

供应商器件封装

SC-70-6

其它名称

296-19088-1

包装

剪切带 (CT)

单位重量

2.500 mg

商标

Texas Instruments

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

6-TSSOP,SC-88,SOT-363

封装/箱体

SC-70-6

工作温度

-40°C ~ 85°C

工厂包装数量

3000

施密特触发器输入

最大工作温度

+ 85 C

最小工作温度

- 40 C

栅极数量

1 Gate

标准包装

1

电压-电源

0.8 V ~ 3.6 V

电流-输出高,低

4mA,4mA

电源电压-最大

3.6 V

电源电压-最小

0.8 V

电路数

1

系列

SN74AUP1G98

输入/输出线数量

2 / 1

输入数

3

输入线路数量

2

输出类型

单端

输出线路数量

1

逻辑类型

可配置多功能

逻辑系列

74AUP

高电平输出电流

- 4 mA

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PDF Datasheet 数据手册内容提取

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE CheckforSamples:SN74AUP1G98 FEATURES 1 • AvailableintheTexasInstrumentsNanoStar™ • WideOperatingV Rangeof0.8Vto3.6V CC Package • Optimizedfor3.3-VOperation • LowStatic-PowerConsumption • 3.6-VI/OToleranttoSupportMixed-Mode (ICC=0.9mAMax) SignalOperation • LowDynamic-PowerConsumption • t =5.3nsMaxat3.3V pd (C =4.6pFTypat3.3V) pd • SuitableforPoint-to-PointApplications • LowInputCapacitance(C =1.5pFTyp) i • Latch-UpPerformanceExceeds100mAPer • LowNoise–OvershootandUndershoot JESD78,ClassII <10%ofV CC • ESDPerformanceTestedPerJESD22 • I SupportsPartial-Power-DownMode off – 2000-VHuman-BodyModel Operation (A114-B,ClassII) • IncludesSchmitt-TriggerInputs – 1000-VCharged-DeviceModel(C101) DBV PACKAGE DCK PACKAGE DRL PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) DRY PACKAGE DSF PACKAGE YFP PACKAGE YZP PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) (TOPVIEW) B 1 6 C B 1 6 C B A11 6A2 C B A11 6A2 C GND 2 5 V GND 2 5 V GND B12 5B2 VCC GND B12 5B2 VCC CC CC A C13 4C2 Y A C13 4C2 Y A 3 4 Y A 3 4 Y Seemechanicaldrawingsfordimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V range CC of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity(seetheverylowundershootandovershootcharacteristicsshowninFigure2). The SN74AUP1G98 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputscanbeconnectedtoV orGND. CC The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and betterswitching-noiseimmunityattheinput. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74AUP1G98 SCES506H–NOVEMBER2003–REVISEDMAY2010 www.ti.com Static-Power Consumption Dynamic-Power Consumption Switching Characteristics (m A) (pF) at 25 MHz† 100% 100% 3.5 80% 80% 3 2.5 4600%% L 3o.g3i-cV† 4600%% L LL3oVV.g3CCi-cV† oltage − V 1.512 Input Output V 20% 20% 0.5 0% AAUUPP 0% AUP 0 −0.5 † Single, dual, and triple gates 0 5 10 15 20 25 30 35 40 45 Time − ns † AUP1G08 data at CL = 15 pF Figure1.AUP–TheLowest-PowerFamily Figure2.ExcellentSignalIntegrity NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. ORDERINGINFORMATION(1) TA PACKAGE(2) POARRDTENRUAMBBLEER MTAORPK-SINIDGE(3) NanoStar –WCSP(DSBGA) Reelof3000 SN74AUP1G98YFPR ___HR_ 0.23-mmLargeBump–YFP(Pb-free) NanoStar –WCSP(DSBGA) Reelof3000 SN74AUP1G98YZPR ___HR_ 0.23-mmLargeBump–YZP(Pb-free) QFN–DRY Reelof5000 SN74AUP1G98DRYR HR –40°Cto85°C uQFN–DSF Reelof5000 SN74AUP1G98DSFR HR SOT(SOT-23)–DBV Reelof3000 SN74AUP1G98DBVR H98_ SOT(SC-70)–DCK Reelof3000 SN74AUP1G98DCKR HR_ SOT(SOT-553)–DRL Reelof4000 SN74AUP1G98DRLR (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) DBV/DCK/DRL:Theactualtop-sidemarkinghasoneadditionalcharacterthatdesignatesthewaferfab/assemblysite. YFP/YZP:Theactualtop-sidemarkinghasthreeprecedingcharacterstodenoteyear,month,andsequencecode,andonefollowing charactertodesignatethewaferfab/assemblysite.Pin1identifierindicatessolder-bumpcomposition(1=SnPb,●=Pb-free). FUNCTIONTABLE INPUTS OUTPUT C B A Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L 2 SubmitDocumentationFeedback Copyright©2003–2010,TexasInstrumentsIncorporated ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 LOGICDIAGRAM(POSITIVELOGIC) 3 A 4 Y 1 B 6 C Table1.FUNCTIONSELECTIONTABLE LOGICFUNCTION FIGURENO. 2-to-1dataselectorwithinvertedoutput Figure3 2-inputNANDgate Figure4 2-inputNORgatewithoneinvertedinput Figure5 2-inputANDgatewithoneinvertedinput Figure5 2-inputNANDgatewithoneinvertedinput Figure6 2-inputORgatewithoneinvertedinput Figure6 2-inputNORgate Figure7 Noninvertedbuffer Figure8 Inverter Figure9 LOGIC CONFIGURATIONS VCC C B 1 6 C B Y 2 5 A A 3 4 Y GND Figure3. 2-to-1DataSelectorWithInvertedOutput WhenCisL,Y=B WhenCisH,Y=A VCC C 1 6 C Y 2 5 A A 3 4 Y GND Figure4. 2-InputNANDGate Copyright©2003–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 SCES506H–NOVEMBER2003–REVISEDMAY2010 www.ti.com VCC C Y A 1 6 C C 2 5 Y A 3 4 Y A GND Figure5. 2-InputNORGateWithOneInvertedInput 2-InputANDGateWithOneInvertedInput VCC C Y B B 1 6 C C 2 5 Y B 3 4 Y GND Figure6. 2-InputNANDGateWithOneInvertedInput 2-InputORGateWithOneInvertedInput VCC C B 1 6 C Y B 2 5 3 4 Y GND Figure7. 2-InputNORGate VCC 1 6 C C Y 2 5 3 4 Y GND Figure8. NoninvertedBuffer 4 SubmitDocumentationFeedback Copyright©2003–2010,TexasInstrumentsIncorporated ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 VCC B 1 6 B Y 2 5 3 4 Y GND Figure9. Inverter Copyright©2003–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 SCES506H–NOVEMBER2003–REVISEDMAY2010 www.ti.com ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 4.6 V CC V Inputvoltagerange(2) –0.5 4.6 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 4.6 V O V Outputvoltagerangeinthehighorlowstate(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±20 mA O ContinuouscurrentthroughV orGND ±50 mA CC DBVpackage 165 DCKpackage 259 DRLpackage 142 q Packagethermalimpedance(3) °C/W JA DSFpackage 300 DRYpackage 234 YFP/YZPpackage 123 T Storagetemperaturerange –65 . °C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. RECOMMENDED OPERATING CONDITIONS(1) MIN MAX UNIT V Supplyvoltage 0.8 3.6 V CC V Inputvoltage 0 3.6 V I V Outputvoltage 0 V V O CC V =0.8V –20 A CC V =1.1V –1.1 CC V =1.4V –1.7 CC I High-leveloutputcurrent OH V =1.65 –1.9 mA CC V =2.3V –3.1 CC V =3V –4 CC V =0.8V 20 mA CC V =1.1V 1.1 CC V =1.4V 1.7 CC I Low-leveloutputcurrent OL V =1.65V 1.9 mA CC V =2.3V 3.1 CC V =3V 4 CC T Operatingfree-airtemperature –40 85 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 6 SubmitDocumentationFeedback Copyright©2003–2010,TexasInstrumentsIncorporated ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 ELECTRICAL CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) T =25°C T =–40°Cto85°C A A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MAX MIN MAX V 0.8V 0.3 0.6 0.3 0.6 T+ 1.1V 0.53 0.9 0.53 0.9 1.4V 0.74 1.11 0.74 1.11 Positive-going V inputthreshold 1.65V 0.91 1.29 0.91 1.29 voltage 2.3V 1.37 1.77 1.37 1.77 3V 1.88 2.29 1.88 2.29 V 0.8V 0.1 0.6 0.1 0.6 T– 1.1V 0.26 0.65 0.26 0.65 1.4V 0.39 0.75 0.39 0.75 Negative-going V inputthreshold 1.65V 0.47 0.84 0.47 0.84 voltage 2.3V 0.69 1.04 0.69 1.04 3V 0.88 1.24 0.88 1.24 ΔV 0.8V 0.07 0.5 0.07 0.5 T 1.1V 0.08 0.46 0.08 0.46 1.4V 0.18 0.56 0.18 0.56 Hysteresis V 1.65V 0.27 0.66 0.27 0.66 (V –V ) T+ T– 2.3V 0.53 0.92 0.53 0.92 3V 0.79 1.31 0.79 1.31 I =–20mA 0.8Vto3.6V V –0.1 V –0.1 OH CC CC I =–1.1mA 1.1V 0.75×V 0.7×V OH CC CC I =–1.7mA 1.4V 1.11 1.03 OH I =–1.9mA 1.65V 1.32 1.3 OH V V OH I =–2.3mA 2.05 1.97 OH 2.3V I =–3.1mA 1.9 1.85 OH I =–2.7mA 2.72 2.67 OH 3V I =–4mA 2.6 2.55 OH I =20mA 0.8Vto3.6V 0.1 0.1 OL I =1.1mA 1.1V 0.3×V 0.3×V OL CC CC I =1.7mA 1.4V 0.31 0.37 OL I =1.9mA 1.65V 0.31 0.35 OL V V OL I =2.3mA 0.31 0.33 OL 2.3V I =3.1mA 0.44 0.45 OL I =2.7mA 0.31 0.33 OL 3V I =4mA 0.44 0.45 OL I Allinputs V =GNDto3.6V 0Vto3.6V 0.1 0.5 mA I I I V orV =0Vto3.6V 0V 0.2 0.6 mA off I O ΔI V orV =0Vto3.6V 0Vto0.2V 0.2 0.6 mA off I O V =GNDor(V to3.6V), I I CC 0.8Vto3.6V 0.5 0.9 mA CC I =0 O ΔI V =V –0.6V(1),I =0 3.3V 40 50 mA CC I CC O 0V 1.5 C V =V orGND pF i I CC 3.6V 1.5 C V =GND 0V 3 pF o O (1) OneinputatV –0.6V,otherinputsatV orGND. CC CC Copyright©2003–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 SCES506H–NOVEMBER2003–REVISEDMAY2010 www.ti.com SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,C =5pF(unlessotherwisenoted)(seeFigure10andFigure11) L T =–40°C PARAMETER FROM TO V TA=25°C Ato85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8V 22.2 1.2V±0.1V 2.7 9.1 13.6 2.2 17 1.5V±0.1V 2 6.4 9.2 1.5 11.1 t A,B,orC Y ns pd 1.8V±0.15V 1.4 5.2 7.2 0.9 8.9 2.5V±0.2V 1.2 3.8 5.3 0.7 6.3 3.3V±0.3V 1 3.1 4.5 0.5 5.3 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,C =10pF(unlessotherwisenoted)(seeFigure10andFigure11) L T =–40°C PARAMETER FROM TO V TA=25°C Ato85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8V 25.4 1.2V±0.1V 5.2 10.4 15.4 4.7 19 1.5V±0.1V 4 7.4 10.5 3.5 12.6 t A,B,orC Y ns pd 1.8V±0.15V 3.1 6 8.3 2.6 10.2 2.5V±0.2V 2.7 4.5 6.1 2.2 7.3 3.3V±0.3V 2.5 3.7 5 2 6 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure10andFigure11) L T =–40°C PARAMETER FROM TO V TA=25°C Ato85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8V 28.7 1.2V±0.1V 3.7 11.5 17 3.2 21.1 1.5V±0.1V 2.8 8.3 11.6 2.3 14 t A,B,orC Y ns pd 1.8V±0.15V 2.1 6.7 9.2 1.6 11.3 2.5V±0.2V 1.8 5 6.7 1.3 8.1 3.3V±0.3V 1.6 4.1 5.5 1.1 6.6 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange,C =30pF(unlessotherwisenoted)(seeFigure10andFigure11) L T =–40°C PARAMETER FROM TO V TA=25°C Ato85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8V 39.7 1.2V±0.1V 5.1 15.3 21.6 4.6 26.8 1.5V±0.1V 3.9 10.9 14.6 3.4 17.6 t A,B,orC Y ns pd 1.8V±0.15V 3.1 8.9 11.5 2.6 14.1 2.5V±0.2V 2.6 6.7 8.4 2.1 10.1 3.3V±0.3V 2.3 5.5 6.9 1.8 8.3 8 SubmitDocumentationFeedback Copyright©2003–2010,TexasInstrumentsIncorporated ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 OPERATING CHARACTERISTICS T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 0.8V 4 1.2V±0.1V 4 1.5V±0.1V 4 C Powerdissipationcapacitance f=10MHz pF pd 1.8V±0.15V 4 2.5V±0.2V 4.3 3.3V±0.3V 4.6 Copyright©2003–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 SCES506H–NOVEMBER2003–REVISEDMAY2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Duration) From Output Under Test CL 1 MW (see Note A) LOAD CIRCUIT VCC = 0.8 V VC±C 0=. 11 .V2 V VC±C 0=. 11 .V5 V VC±C 0 =.1 15. 8V V VC±C 0=. 22 .V5 V VC±C 0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC tw VCC Input VCC/2 VCC/2 VI 0 V Input VM VM 0 V VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL Output VM VM VOH VCC VOL Timing Input VCC/2 0 V tPHL tPLH VOH tsu th Output VM VM VCC VOL Data Input VCC/2 VCC/2 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS INVERTING AND NONINVERTING OUTPUTS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , slew rate ≥ 1 V/ns. C. The outputs are measured one at a time, with one transition per measurement. D. tPLH and tPHL are the same as tpd. E. All parameters and waveforms are not applicable to all devices. Figure10. LoadCircuitandVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2003–2010,TexasInstrumentsIncorporated ProductFolderLink(s):SN74AUP1G98

SN74AUP1G98 www.ti.com SCES506H–NOVEMBER2003–REVISEDMAY2010 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC 5 kW S1 From Output Under Test GND TEST S1 CL 5 kW tPLZ/tPZL 2 × VCC (see Note A) tPHZ/tPZH GND LOAD CIRCUIT VCC = 0.8 V VC±C 0=. 11 .V2 V VC±C 0=. 11 .V5 V VC±C 0 =.1 15. 8V V VC±C 0=. 22 .V5 V VC±C 0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC VD 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCC Output Control VCC/2 VCC/2 0 V tPZL tPLZ Output Waveform 1 VCC S1 at 2 × VCC VCC/2 VOL + VD (see Note B) VOL tPZH tPHZ Output WSa1v eafto GrmN D2 VCC/2 VOH - VD VOH ≈0 V (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure11. LoadCircuitandVoltageWaveforms Copyright©2003–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):SN74AUP1G98

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AUP1G98DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 H98R & no Sb/Br) SN74AUP1G98DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HRR & no Sb/Br) SN74AUP1G98DCKT ACTIVE SC70 DCK 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HRR & no Sb/Br) SN74AUP1G98DRLR ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (HR7, HRR) & no Sb/Br) SN74AUP1G98DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HR & no Sb/Br) SN74AUP1G98DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 HR & no Sb/Br) SN74AUP1G98YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 (HR7, HRN) & no Sb/Br) SN74AUP1G98YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 HRN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUP1G98DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G98DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74AUP1G98DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74AUP1G98DRLR SOT-5X3 DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SN74AUP1G98DRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AUP1G98DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74AUP1G98DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74AUP1G98YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1 SN74AUP1G98YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUP1G98DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74AUP1G98DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74AUP1G98DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74AUP1G98DRLR SOT-5X3 DRL 6 4000 184.0 184.0 19.0 SN74AUP1G98DRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0 SN74AUP1G98DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G98DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74AUP1G98YFPR DSBGA YFP 6 3000 220.0 220.0 35.0 SN74AUP1G98YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DRL0006A SOT - 0.6 mm max height SCALE 8.000 PLASTIC SMALL OUTLINE 1.7 1.5 PIN 1 A ID AREA 1 6 4X 0.5 1.7 1.5 2X 1 NOTE 3 4 3 B 11..31 6X 00..31 00..0050 TYP 0.6 MAX C SEATING PLANE 0.18 6X 0.08 SYMM 0.05 C SYMM 0.27 6X 0.15 0.1 C A B 0.4 6X 0.2 0.05 4223266/A 09/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DRL0006A SOT - 0.6 mm max height PLASTIC SMALL OUTLINE 6X (0.67) SYMM 1 6X (0.3) 6 SYMM 4X (0.5) 4 3 (R0.05) TYP (1.48) LAND PATTERN EXAMPLE SCALE:30X 0.05 MAX 0.05 MIN AROUND AROUND SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDERMASK DETAILS 4223266/A 09/2016 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DRL0006A SOT - 0.6 mm max height PLASTIC SMALL OUTLINE 6X (0.67) SYMM 1 6X (0.3) 6 SYMM 4X (0.5) 4 3 (R0.05) TYP (1.48) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X 4223266/A 09/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE YFP0006 DSBGA - 0.5 mm max height SCALE 10.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.13 BALL TYP 0.05 C 0.4 TYP SYMM C D: Max = 1.19 mm, Min = 1.13 mm 0.8 TYP B SYMM E: Max = 0.79 mm, Min = 0.73 mm 0.4 TYP A 0.25 6X 0.21 1 2 0.015 C A B 4223410/A 11/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YFP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 6X ( 0.23) 1 2 A (0.4) TYP B SYMM C SYMM LAND PATTERN EXAMPLE SCALE:50X ( 0.23) 0.05 MAX 0.05 MIN METAL UNDER METAL SOLDER MASK SOLDER MASK ( 0.23) OPENING SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223410/A 11/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YFP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 6X ( 0.25) (R0.05) TYP 1 2 A (0.4) TYP B SYMM METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 4223410/A 11/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com

EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0006 DSBGA - 0.5 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.5 MAX C SEATING PLANE 0.19 BALL TYP 0.05 C 0.15 0.5 TYP C SYMM 1 D: Max = 1.418 mm, Min =1 .358 mm B TYP 0.5 E: Max = 0.918 mm, Min =0 .858 mm TYP A 0.25 1 2 6X 0.21 SYMM 0.015 C A B 4219524/A 06/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFreeTM package configuration. www.ti.com

EXAMPLE BOARD LAYOUT YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.225) 1 2 A (0.5) TYP B SYMM C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.225) 0.05 MAX 0.05 MIN METAL METAL UNDER MASK SOLDER MASK ( 0.225) OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219524/A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com

EXAMPLE STENCIL DESIGN YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219524/A 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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