SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – RSENV7IS4EADU MPAY1 G203220 SCES580K – JUNE 2004 – REVISED MAY 2020 SN74AUP1G32 Low-Power Single 2-Input Positive-OR Gate 1 Features 2 Applications • Available in the ultra-small 0.64 mm2 package • ATCA solutions (DPW) with 0.5-mm pitch • Active noise cancellation (ANC) • Low static-power consumption • Barcode scanner the end of the datasheet. (ICC = 0.9 µA Max) • Blood pressure monitor • Low dynamic-power consumption • CPAP machine (C = 4.3 pF Typ at 3.3 V) pd • Cable solutions • Low input capacitance (C = 1.5 pF Typ) I • DLP 3D machine vision, hyperspectral imaging, • Low noise – overshoot and undershoot optical networking, and spectroscopy <10% of V CC • E-Book • I Supports live insertion, partial-power-down off • Embedded PC mode, and back drive protection • Field transmitter: temperature or pressure sensor • Input hysteresis allows slow input transition and • Fingerprint biometrics better switching noise immunity at the • HVAC: heating, ventilating, and air conditioning input (V = 250 mV typ at 3.3 V) hys • Network-attached storage (NAS) • Wide operating V range of 0.8 V to 3.6 V CC • Server motherboard and PSU • Optimized for 3.3-V operation • Software defined radio (SDR) • 3.6-V I/O Tolerant to support mixed-mode signal operation • TV: high-definition (HDTV), LCD, and Digital • t = 4.6 ns Max at 3.3 V • Video communications system pd • Suitable for point-to-point applications • Wireless data access card, headset, keyboard, mouse, and LAN card • Latch-up performance exceeds 100 mA Per JESD 78, Class II • X-ray: baggage scanner, medical, and dental • ESD performance tested Per JESD 22 3 Description – 2000-V Human-body model This single 2-input positive-OR gate performs the (A114-B, Class II) Boolean function Y=A·Bor Y= A+B in positive – 1000-V Charged-device model (C101) logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) SOT (5) 1.60 mm × 1.20 mm USON (6) 1.45 mm × 1.00 mm SN74AUP1G32 X2SON (4) 0.80 mm × 0.80 mm DSBGA (6) 1.19 mm × 0.79 mm DSBGA (5) 1.41 mm × 0.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. A Y B Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyrighint t©e l2le0c2t0u Tael xparso Ipnesrtrtuym meanttste Irnsc oarnpdor aottehder important disclaimers. PRODUCTION DATA. Submit Document Feedback 1

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com Table of Contents 1 Features............................................................................1 8 Detailed Description......................................................11 2 Applications.....................................................................1 8.1 Overview...................................................................11 3 Description.......................................................................1 8.2 Functional Block Diagram.........................................11 4 Revision History..............................................................2 8.3 Feature Description...................................................11 5 Pin Configuration and Functions...................................3 8.4 Device Functional Modes..........................................11 6 Specifications..................................................................4 9 Application and Implementation..................................12 6.1 Absolute Maximum Ratings........................................4 9.1 Application Information.............................................12 6.2 Handling Ratings.........................................................4 9.2 Typical Application....................................................12 6.3 Recommended Operating Conditions.........................4 10 Power Supply Recommendations..............................13 6.4 Thermal Information....................................................5 11 Layout...........................................................................13 6.5 Electrical Characteristics.............................................6 11.1 Layout Guidelines...................................................13 6.6 Switching Characteristics, C = 5 pF..........................6 11.2 Layout Example......................................................13 L 6.7 Switching Characteristics, C = 10 pF........................7 12 Device and Documentation Support..........................14 L 6.8 Switching Characteristics, C = 15 pF........................7 12.1 Receiving Notification of Documentation Updates..14 L 6.9 Switching Characteristics, C = 30 pF........................7 12.2 Support Resources.................................................14 L 6.10 Operating Characteristics.........................................8 12.3 Trademarks.............................................................14 6.11 Typical Characteristics..............................................8 12.4 Electrostatic Discharge Caution..............................14 7 Parameter Measurement Information............................9 12.5 Glossary..................................................................14 7.1 Propagation Delays, Setup and Hold Times, and 13 Mechanical, Packaging, and Orderable Pulse Width...................................................................9 Information....................................................................14 7.2 Enable and Disable Times........................................10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (September 2019) to Revision K (May 2020) Page • Corrected DPW package image description to "DPW Package X2SON 5-pins (Transparent Top View)"..........3 • Updated DPW package image...........................................................................................................................3 Changes from Revision I (June 2014) to Revision J (September 2019) Page • Changed format of Pin Configuration images to allow for HTML search function .............................................3 • Corrected YFP package pin descriptors in the Pin Functions table ...................................................................3 • Added Thermal Information for the DPW package ............................................................................................5 Changes from Revision H (August 2012) to Revision I (June 2014) Page • Updated document to new TI data sheet format.................................................................................................1 • Removed Ordering Information table..................................................................................................................1 • Added Applications.............................................................................................................................................1 • Added Handling Ratings table............................................................................................................................4 • Added Thermal Information table.......................................................................................................................5 • Added Typical Characteristics............................................................................................................................8 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 5 Pin Configuration and Functions A 1 5 V CC A 1 5 VCC B 2 GND 3 4 Y B 2 Figure 5-2. DRL Package SOT 5-pin (Top View) GND 3 4 Y Figure 5-1. DBV Package SOT 5-pin (Top View) A 1 6 VCC A 1 6 VCC B 2 5 N.C. B 2 5 N.C. GND 3 4 Y GND 3 4 Y Figure 5-3. DSF Package SON 6-pin (Transparent N.C. - No internal connection Top View) Figure 5-4. DRY Package SON 6-pin (Transparent Top View) A 1 5 VCC A A11 5A2 VCC B B12 B 2 GND C13 4C2 Y GND 3 4 Y Figure 5-6. YZP Package DSBGA 5-balls (Transparent Top View) Figure 5-5. DCK Package SC70 5-pin (Top View) A V A11 6A2 CC B 1 5 VCC B B12 5B2 DNU GND C13 4C2 Y 3 DNU - Do Not Use GND Figure 5-8. YFP Package DSBGA 6-balls A 2 4 Y (Transparent Top View) Not to scale See mechanical drawings at the end of the data sheet for all package dimensions Figure 5-7. DPW Package X2SON 5-pins (Transparent Top View) Pin Functions PIN DRL, I/O DESCRIPTION NAME DCK, DPW DRY, DSF YZP YFP DBV A 1 2 1 A1 A1 I Input A B 2 1 2 B1 B1 I Input B GND 3 3 3 C1 C1 – Ground Y 4 4 4 C2 C2 O Output Y VCC 5 5 6 A2 A2 – Power Pin Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT V Supply voltage range –0.5 4.6 V CC V Input voltage range(2) –0.5 4.6 V I V Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V O V Voltage range applied to any output in the high or low state(2) –0.5 V + 0.5 V O CC I Input clamp current V < 0 –50 mA IK I I Output clamp current V < 0 –50 mA OK O I Continuous output current ±20 mA O Continuous current through V or GND ±50 mA CC (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 Handling Ratings MIN MAX UNIT T Storage temperature range –65 125 °C stg Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000 pins(1) V Electrostatic discharge V (ESD) Charged device model (CDM), per JEDEC specification 0 1000 JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions see (1) MIN MAX UNIT V Supply voltage 0.8 3.6 V CC V = 0.8 V V CC CC V = 1.1 V to 1.95 V 0.65 × V CC CC V High-level input voltage V IH V = 2.3 V to 2.7 V 1.6 CC V = 3 V to 3.6 V 2 CC V = 0.8 V 0 CC V = 1.1 V to 1.95 V 0.35 × V CC CC V Low-level input voltage V IL V = 2.3 V to 2.7 V 0.7 CC V = 3 V to 3.6 V 0.9 CC V Input voltage 0 3.6 V I V Output voltage 0 V V O CC V = 0.8 V –20 µA CC V = 1.1 V –1.1 CC V = 1.4 V –1.7 CC I High-level output current OH V = 1.65 V –1.9 mA CC V = 2.3 V –3.1 CC V = 3 V –4 CC 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 see (1) MIN MAX UNIT V = 0.8 V 20 µA CC V = 1.1 V 1.1 CC V = 1.4 V 1.7 CC I Low-level output current OL V = 1.65 V 1.9 mA CC V = 2.3 V 3.1 CC V = 3 V 4 CC Δt/Δv Input transition rise and fall rate V = 0.8 V to 1.95 V 200 ns/V CC T Operating free-air temperature –40 85 °C A (1) All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, CC Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information DBV DCK DRL DSF DRY DPW THERMAL METRIC(1) UNIT 5 PINS 5 PINS 5 PINS 6 PINS 6 PINS 5 PINS Junction-to-ambient thermal resistance R 271.4 338.4 349.7 407.1 554.9 492.1 °C/W θJA (standard data sheet value) Junction-to-case (top) thermal resistance R 213.5 110.6 120.5 232.0 385.4 232.6 °C/W θJC(top) (standard data sheet value) Junction-to-board thermal resistance R 108.2 118.8 171.4 306.9 388.2 355.4 °C/W θJB (standard data sheet value) Junction-to-top characterization parameter ψ 89.3 3.0 10.8 40.3 159.0 37.4 °C/W JT (standard data sheet value) Junction-to-board characterization ψ 107.6 117.8 169.4 306.0 384.1 353.9 °C/W JB parameter (standard data sheet value) Junction-to-case (bottom) thermal ψ – – – – – 147.9 °C/W JC(bot) resistance (standard data sheet value) (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) T = 25°C T = –40°C to 85°C A A PARAMETER TEST CONDITIONS V UNIT CC MIN TYP MAX MIN MAX I = –20 µA 0.8 V to 3.6 V V – 0.1 V – 0.1 OH CC CC I = –1.1 mA 1.1 V 0.75 × V 0.7 × V OH CC CC I = –1.7 mA 1.4 V 1.11 1.03 OH I = –1.9 mA 1.65 V 1.32 1.3 OH V V OH I = –2.3 mA 2.05 1.97 OH 2.3 V I = –3.1 mA 1.9 1.85 OH I = –2.7 mA 2.72 2.67 OH 3 V I = –4 mA 2.6 2.55 OH I = 20 µA 0.8 V to 3.6 V 0.1 0.1 OL I = 1.1 mA 1.1 V 0.3 × V 0.3 × V OL CC CC I = 1.7 mA 1.4 V 0.31 0.37 OL I = 1.9 mA 1.65 V 0.31 0.35 OL V V OL I = 2.3 mA 0.31 0.33 OL 2.3 V I = 3.1 mA 0.44 0.45 OL I = 2.7 mA 0.31 0.33 OL 3 V I = 4 mA 0.44 0.45 OL I A or B input V = GND to 3.6 V 0 V to 3.6 V 0.1 0.5 µA I I I V or V = 0 V to 3.6 V 0 V 0.2 0.6 µA off I O ΔI V or V = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µA off I O V = GND or (V to 3.6 V), I I CC 0.8 V to 3.6 V 0.5 0.9 µA CC I = 0 O V = V – 0.6 V(1), ΔI I CC 3.3 V 40 50 µA CC I = 0 O 0 V 1.5 C V = V or GND pF i I CC 3.6 V 1.5 C V = GND 0 V 3 pF o O (1) One input at V – 0.6 V, other input at V or GND. CC CC 6.6 Switching Characteristics, C = 5 pF L over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 and Figure 7-2) T = –40°C PARAMETER FROM TO V TA = 25°C Ato 85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8 V 18 1.2 V ± 0.1 V 2.6 7.3 13.5 2.1 16.8 1.5 V ± 0.1 V 1.4 5.2 9.1 0.9 11 t A or B Y ns pd 1.8 V ± 0.15 V 1 4.2 7 0.5 8.8 2.5 V ± 0.2 V 1 3 4.7 0.5 6 3.3 V ± 0.3 V 1 2.4 3.7 0.5 4.6 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 6.7 Switching Characteristics, C = 10 pF L over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 and Figure 7-2) T = –40°C PARAMETER FROM TO V TA = 25°C Ato 85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8 V 21 1.2 V ± 0.1 V 1.5 8.5 15.4 1 18.4 1.5 V ± 0.1 V 1 6.2 10.4 0.5 12 t A or B Y ns pd 1.8 V ± 0.15 V 1 5 8.1 0.5 9.6 2.5 V ± 0.2 V 1 3.6 5.5 0.5 6.6 3.3 V ± 0.3 V 1 2.9 4.4 0.5 5 6.8 Switching Characteristics, C = 15 pF L over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 and Figure 7-2) T = –40°C PARAMETER FROM TO V TA = 25°C Ato 85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8 V 24 1.2 V ± 0.1 V 3.6 9.9 17 3.1 21.1 1.5 V ± 0.1 V 2.3 7.2 11.5 1.8 13.9 t A or B Y ns pd 1.8 V ± 0.15 V 1.6 5.8 9.1 1.1 11.2 2.5 V ± 0.2 V 1 4.3 6.2 0.5 7.8 3.3 V ± 0.3 V 1 3.4 5 0.5 6.2 6.9 Switching Characteristics, C = 30 pF L over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1 and Figure 7-2) T = –40°C PARAMETER FROM TO V TA = 25°C Ato 85°C UNIT (INPUT) (OUTPUT) CC MIN TYP MAX MIN MAX 0.8 V 32.8 1.2 V ± 0.1 V 4.9 13.1 21.6 4.4 26.7 1.5 V ± 0.1 V 3.4 9.5 14.6 2.9 17.6 t A or B Y ns pd 1.8 V ± 0.15 V 2.5 7.7 11.4 2 14.1 2.5 V ± 0.2 V 1.8 5.7 7.9 1.3 9.9 3.3 V ± 0.3 V 1.5 4.7 6.4 1 7.8 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 6.10 Operating Characteristics T = 25°C A PARAMETER TEST CONDITIONS V TYP UNIT CC 0.8 V 4.1 1.2 V ± 0.1 V 4.1 1.5 V ± 0.1 V 4.1 C Power dissipation capacitance f = 10 MHz pF pd 1.8 V ± 0.15 V 4.1 2.5 V ± 0.2 V 4.2 3.3 V ± 0.3 V 4.3 6.11 Typical Characteristics 30 7 TPD in ns TPD in ns 25 6 5 20 D (ns) 15 D (ns) 4 TP TP 3 10 2 5 1 0 0 0 1 2 3 4 -50 0 50 100 150 VCC (V) D001 Temperature (°C) D001 Figure 6-1. TPD vs VCC, 15 pF Load Figure 6-2. Temperature 1.8 V, 15 pF Load 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 7 Parameter Measurement Information 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width From Output Under Test CL 1 MΩ (see NoteA) LOAD CIRCUIT VCC= 0.8 V VC±C0=. 11 .V2 V VC±C0=. 11 .V5 V VC±C0=.1 15. 8V V VC±C0=. 22 .V5 V VC±C0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC tw VCC Input VCC/2 VCC/2 VI 0 V Input VM VM 0 V VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL Output VM VM VOH VCC VOL Timing Input VCC/2 0 V tPHL tPLH VOH tsu th Output VM VM VCC VOL Data Input VCC/2 VCC/2 0 V VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES VOLTAGE WAVEFORMS INVERTINGAND NONINVERTING OUTPUTS SETUPAND HOLD TIMES A. C includes probe and jig capacitance. L B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, O t and t = 3 ns. r f C. The outputs are measured one at a time, with one transition per measurement. D. t and t are the same as t . PLH PHL pd E. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 7.2 Enable and Disable Times 2×VCC S1 5 kΩ From Output Under Test GND TEST S1 CL tPLZ/tPZL 2×VCC 5 kΩ (see NoteA) tPHZ/tPZH GND LOAD CIRCUIT VCC= 0.8 V VC±C0=. 11 .V2 V VC±C0=. 11 .V5 V VC±C0=.1 15. 8V V VC±C0=. 22 .V5 V VC±C0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC VD 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCC Output Control VCC/2 VCC/2 0 V tPZL tPLZ Output Waveform 1 VCC S1 at 2×VCC VCC/2 VOL+ VΔ (see Note B) VOL tPZH tPHZ Output WSa1v eafto GrmN D2 VCC/2 VOH−VΔ VOH ≈0 V (see Note B) VOLTAGE WAVEFORMS ENABLEAND DISABLE TIMES LOW-AND HIGH-LEVELENABLING A. C includes probe and jig capacitance. L C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, O t and t = 3 ns. r f D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G. All parameters and waveforms are not applicable to all devices. Figure 7-2. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 8 Detailed Description 8.1 Overview This single 2-input positive-OR gate that operates from 0.8 V to 3.6 V and performs the Boolean function Y=A·Bor Y= A+B in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. 8.2 Functional Block Diagram A Y B 8.3 Feature Description • Wide operating V range of 0.8 V to 3.6 V CC • 3.6-V I/O tolerant to support down translation • Input hysteresis allows slow input transition and better switching noise immunity at the input • I feature allows voltages on the inputs and outputs when V is 0 V off CC • Low noise due to slower edge rates 8.4 Device Functional Modes Table 8-1. Function Table INPUTS OUTPUT A B Y L L L L H H H L H H H H Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It has a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive produces slower edges and prevents overshoot and undershoot on the outputs. The AUP family of single gate logic makes excellent translators for the new lower voltage Micro- processors that typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that are still powered by 3.3 V to the new uC power levels. 9.2 Typical Application 3.3-V Bus driver VCC 1 V regulated 0.1 µF 1-V Micro Processor Driver µC Figure 9-1. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. 9.2.2 Detailed Design Procedure 1. Recommended Input conditions • Rise time and fall time specifications. See (Δt/ΔV) in Recommended Operating Conditions table. • Specified high and low levels. See (V and V ) in Recommended Operating Conditions table. IH IL • Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid V CC 2. Recommend output conditions • Load currents should not exceed 20 mA on the output and 50 mA total for the part • Outputs should not be pulled above V CC 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

SN74AUP1G32 www.ti.com SCES580K – JUNE 2004 – REVISED MAY 2020 9.2.3 Application Curves Switching Characteristics at25MHz† 3.5 3 2.5 V Input Output − 2 e g 1.5 a olt 1 V 0.5 0 −0.5 0 5 10 15 20 25 30 35 40 45 Time−ns † AUP1G08dataatCL=15pF Figure 9-2. AUP – The Lowest-Power Family Figure 9-3. Excellent Signal Integrity 10 Power Supply Recommendations The power supply can be any voltage between the Min and Max supply voltage rating located in the Recommended Operating Conditions table. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, 0.1 μF is recommended and if there are multiple V terminals then .01 μF or .022 μF is recommended CC for each power terminal. It is ok to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more convenient. It is generally OK to float outputs unless the CC part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float when disabled. 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13

SN74AUP1G32 SCES580K – JUNE 2004 – REVISED MAY 2020 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74AUP1G32DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 H32R & no Sb/Br) SN74AUP1G32DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 H32R & no Sb/Br) SN74AUP1G32DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (HG5, HGF, HGK, HG & no Sb/Br) R) SN74AUP1G32DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (HG5, HGF, HGK, HG & no Sb/Br) R) SN74AUP1G32DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (HG5, HGR) & no Sb/Br) SN74AUP1G32DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 F4 & no Sb/Br) SN74AUP1G32DRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (HG7, HGR) & no Sb/Br) SN74AUP1G32DRY2 ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HG & no Sb/Br) SN74AUP1G32DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 HG & no Sb/Br) SN74AUP1G32DSF2 ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HG & no Sb/Br) SN74AUP1G32DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 HG & no Sb/Br) SN74AUP1G32YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM HGN & no Sb/Br) SN74AUP1G32YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 HGN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUP1G32DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G32DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G32DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74AUP1G32DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74AUP1G32DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74AUP1G32DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74AUP1G32DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3 SN74AUP1G32DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AUP1G32DRLR SOT-5X3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SN74AUP1G32DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3 SN74AUP1G32DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74AUP1G32DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 SN74AUP1G32DSFR SON DSF 6 5000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2 SN74AUP1G32YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1 SN74AUP1G32YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUP1G32DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUP1G32DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74AUP1G32DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74AUP1G32DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AUP1G32DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AUP1G32DCKT SC70 DCK 5 250 202.0 201.0 28.0 SN74AUP1G32DPWR X2SON DPW 5 3000 205.0 200.0 33.0 SN74AUP1G32DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0 SN74AUP1G32DRLR SOT-5X3 DRL 5 4000 184.0 184.0 19.0 SN74AUP1G32DRY2 SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G32DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G32DSF2 SON DSF 6 5000 184.0 184.0 19.0 SN74AUP1G32DSFR SON DSF 6 5000 210.0 185.0 35.0 SN74AUP1G32YFPR DSBGA YFP 6 3000 220.0 220.0 35.0 SN74AUP1G32YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DPW0005A X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD B 0.85 A 0.75 PIN 1 INDEX AREA 0.85 0.75 0.4 MAX C SEATING PLANE NOTE 3 (0.1) 0.05 (0.25) 4X (0.05) 0.00 0.25 0.1 2 4 NOTE 3 2X 3 2X (0.26) 0.48 5 1 0.27 0.27 4X 0.17 0.17 0.1 C A B (0.06) 0.05 C 0.32 3X 0.23 4223102/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. www.ti.com

EXAMPLE BOARD LAYOUT DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM ( 0.1) 4X (0.42) VIA 0.05 MIN ALL AROUND 1 TYP 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP SOLDER MASK 4X (0.06) OPENING, TYP ( 0.25) (0.21) TYP METAL UNDER EXPOSED METAL SOLDER MASK CLEARANCE TYP LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X 4223102/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.06) 5 4X (0.22) 1 ( 0.24) 4X (0.26) SYMM (0.21) (0.48) TYP SOLDER MASK 3 EDGE 2 4 (R0.05) TYP SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0005 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP C SYMM 1 B D: Max = 1.418 mm, Min =1 .358 mm TYP 0.5 TYP E: Max = 0.918 mm, Min =0 .858 mm A 0.25 5X 1 2 0.21 0.015 C A B SYMM 4219492/A 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.23) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219492/A 05/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL SYMM TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219492/A 05/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

PACKAGE OUTLINE YFP0006 DSBGA - 0.5 mm max height SCALE 10.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.13 BALL TYP 0.05 C 0.4 TYP SYMM C D: Max = 1.19 mm, Min = 1.13 mm 0.8 TYP B SYMM E: Max = 0.79 mm, Min = 0.73 mm 0.4 TYP A 0.25 6X 0.21 1 2 0.015 C A B 4223410/A 11/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YFP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 6X ( 0.23) 1 2 A (0.4) TYP B SYMM C SYMM LAND PATTERN EXAMPLE SCALE:50X ( 0.23) 0.05 MAX 0.05 MIN METAL UNDER METAL SOLDER MASK SOLDER MASK ( 0.23) OPENING SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223410/A 11/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YFP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 6X ( 0.25) (R0.05) TYP 1 2 A (0.4) TYP B SYMM METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 4223410/A 11/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com

EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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