Product Order Technical Tools & Support & Folder Now Documents Software Community SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 SN74AUP1G17 Low-Power Single Schmitt-Trigger Buffer 1 Features 3 Description • Latch-UpPerformanceExceeds100mAPer The AUP family of devices is TI's premier solution to 1 the industry's low-power needs in battery-powered JESD78,ClassII portable applications. This family ensures a very low • ESDPerformanceTestedPerJESD22 static- and dynamic-power consumption across the – 2000-VHuman-BodyModel entire V range of 0.8 V to 3.6 V, resulting in CC (A114-B,ClassII) increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest- – 1000-VCharged-DeviceModel(C101) PowerFamilyandExcellentSignalIntegrity). • AvailableintheTexasInstruments NanoStar™ Package This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input • LowStatic-PowerConsumption transition and better switching-noise immunity at the (I =0.9µAMaximum) CC input. • LowDynamic-PowerConsumption NanoStar™ package technology is a major (C =4.4pFTypicalat3.3V) pd breakthrough in IC packaging concepts, using the die • LowInputCapacitance(Ci=1.5pFTypical) asthepackage. • LowNoise–OvershootandUndershoot This device is fully specified for partial-power-down <10%ofV CC applications using I . The I circuitry disables the off off • IoffSupportsPartial-Power-DownModeOperation outputs when the device is powered down. This • IncludesSchmitt-TriggerInputs inhibits current backflow into the device which preventsdamagetothedevice. • WideOperatingV Rangeof0.8Vto3.6V CC • Optimizedfor3.3-VOperation DeviceInformation(1) • 3.6-VI/OToleranttoSupportMixed-ModeSignal PARTNUMBER PACKAGE BODYSIZE(NOM) Operation SN74AUP1G17DBV SOT-23(5) 1.60mm×2.90mm • t =5.1nsMaximumat3.3V pd SN74AUP1G17DCK SC70(5) 1.25mm×2.00mm • SuitableforPoint-to-PointApplications SN74AUP1G17DRL SOT-5X3(5) 1.60mm×1.20mm SN74AUP1G17DRY SON(6) 1.00mm×1.45mm 2 Applications SN74AUP1G17DSF SON(6) 1.00mm×1.00mm • GridInfrastructure SN74AUP1G17YFP DSBGA(4) 0.76mm×0.76mm • PC& Notebooks SN74AUP1G17YZP DSBGA(5) 0.89mm×1.39mm • Tablets SN74AUP1G17DPW X2SON(5) 0.80mm×0.80mm • FactoryAutomation &Control (1) For all available packages, see the orderable addendum at theendofthedatasheet. • Gaming • Server LogicDiagram(PositiveLogic) LogicDiagram(PositiveLogic) (DBV,DCK,DPW,DRL,DRT,DRY,andYZP (YFPPackage) Packages) 1 3 A Y 2 4 A Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8 DetailedDescription............................................ 12 2 Applications........................................................... 1 8.1 Overview.................................................................12 3 Description............................................................. 1 8.2 FunctionalBlockDiagrams.....................................12 4 RevisionHistory..................................................... 2 8.3 FeatureDescription.................................................12 8.4 DeviceFunctionalModes........................................13 5 PinConfigurationandFunctions......................... 3 9 ApplicationandImplementation........................ 14 6 Specifications......................................................... 4 9.1 ApplicationInformation............................................14 6.1 AbsoluteMaximumRatings......................................4 9.2 TypicalApplication..................................................14 6.2 ESDRatings..............................................................4 10 PowerSupplyRecommendations..................... 16 6.3 RecommendedOperatingConditions.......................4 6.4 ThermalInformation..................................................5 11 Layout................................................................... 16 6.5 ElectricalCharacteristics...........................................5 11.1 LayoutGuidelines.................................................16 6.6 SwitchingCharacteristics:C =5pF........................7 11.2 LayoutExample....................................................16 L 6.7 SwitchingCharacteristics:C =10pF......................8 12 DeviceandDocumentationSupport................. 17 L 6.8 SwitchingCharacteristics:C =15pF......................8 12.1 DocumentationSupport........................................17 L 6.9 SwitchingCharacteristics:C =30pF......................9 12.2 ReceivingNotificationofDocumentationUpdates17 L 6.10 OperatingCharacteristics........................................9 12.3 CommunityResources..........................................17 6.11 TypicalCharacteristics............................................9 12.4 Trademarks...........................................................17 7 ParameterMeasurementInformation................10 12.5 ElectrostaticDischargeCaution............................17 7.1 PropagationDelays,SetupandHoldTimes,and 12.6 Glossary................................................................17 PulseDuration.........................................................10 13 Mechanical,Packaging,andOrderable 7.2 EnableandDisableTimes......................................11 Information........................................................... 17 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionI(March2010)toRevisionJ Page • AddedApplications,DeviceInformationtable,PinConfigurationandFunctionssection,ESDRatingstable,Thermal Informationtable,FeatureDescriptionsection,ApplicationandImplementationsection,PowerSupply Recommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical, Packaging,andOrderableInformationsection...................................................................................................................... 1 • DeletedOrderingInformationtable,seeMechanical,Packaging,andOrderableInformationattheendofthedata sheet ...................................................................................................................................................................................... 1 2 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 5 Pin Configuration and Functions DBVPackage 5-PinSOT-23 DCKPackage TopView 5-PinSC70 TopView N.C. 1 5 VCC N.C. 1 5 VCC A 2 A 2 GND 3 4 Y GND 3 4 Y N.C.–Nointernalconnection. DRLPackage 5-PinSOT-5X3 DPWPackage TopView 5-PinX2SON TopView N.C. 1 5 VCC NC V GND CC A 2 A Y GND 3 4 Y DRYPackage 6-PinSON DSFPackage TopView 6-PinSON TopView N.C. 1 6 V CC N.C. 1 6 V CC A 2 5 N.C. A 2 5 N.C. GND 3 4 Y GND 3 4 Y YFPPackage 4-PinDSBGA YZPPackage BottomView 5-PinDSBGA BottomView 1 2 1 2 B GND Y C GND Y A A VCC B A Not to scale Seemechanicaldrawingsfordimensions. A DNU VCC Not to scale DNU–Donotuse PinFunctions PIN DBV,DCK, I/O DESCRIPTION NAME DRY,DSF YFP YZP DRL,DPW A 2 2 A1 B1 I Input DNU — — — A1 — Donotuse GND 3 3 B1 C1 — Ground 1 N.C. 1 — — — Noconnection 5 V 5 6 A2 A2 — Positivesupply CC Y 4 4 B2 C2 O Output Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 4.6 V CC V Inputvoltage(2) –0.5 4.6 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 4.6 V O V Outputvoltagerangeinthehighorlowstate(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±20 mA O ContinuouscurrentthroughV orGND ±50 mA CC T Junctiontemperature 150 °C j T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions See(1) MIN MAX UNIT V Supplyvoltage 0.8 3.6 V CC V Inputvoltage 0 3.6 V I V Outputvoltage 0 V V O CC V =0.8V –20 µA CC V =1.1V –1.1 CC V =1.4V –1.7 I (2) High-leveloutputcurrent CC OH V =1.65 –1.9 mA CC V =2.3V –3.1 CC V =3V –4 CC V =0.8V 20 µA CC V =1.1V 1.1 CC V =1.4V 1.7 I (2) Low-leveloutputcurrent CC OL V =1.65V 1.9 mA CC V =2.3V 3.1 CC V =3V 4 CC T Operatingfree-airtemperature –40 85 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeeImplicationsofSloworFloating CC CMOSInputs. (2) Definedbythesignal-integrityrequirementsanddesign-goalpriorities 4 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 6.4 Thermal Information SN74AUP1G17 THERMALMETRIC(1) DBV DCK DRL DPW DRY DSF YFP YZP UNIT (SOT-23) (SC70) (SOT-5X3) (X2SON) (SON) (SON) (DSBGA) (DSBGA) 5PINS 5PINS 5PINS 5PINS 6PINS 6PINS 4PINS 5PINS Junction-to-ambientthermal RθJA resistance 267.2 284.1 294.7 489.2 347.8 386.2 179.3 146.2 °C/W Junction-to-case(top)thermal RθJC(top) resistance 191.9 208.5 132.5 226.3 237.7 192.9 2.8 1.4 °C/W Junction-to-boardthermal RθJB resistance 101.1 103.1 143.6 352.9 210.6 242.2 58.3 39.3 °C/W Junction-to-topcharacterization ψJT parameter 83.0 76.6 14.5 38.2 64.4 28.9 1.1 0.7 °C/W Junction-to-board ψJB characterizationparameter 100.8 102.3 144.1 352.1 210.6 241.9 58.6 39.8 °C/W Junction-to-case(bottom) RθJC(bot) thermalresistance N/A N/A N/A 150.8 N/A N/A N/A N/A °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC T =25°C 0.3 0.6 A 0.8V T =–40°Cto+85°C 0.3 0.6 A T =25°C 0.53 0.9 A 1.1V T =–40°Cto+85°C 0.53 0.9 A T =25°C 0.74 1.11 A VT+ 1.4V Positive-going TA=–40°Cto+85°C 0.74 1.11 V inputthreshold T =25°C 0.91 1.29 A voltage 1.65V T =–40°Cto+85°C 0.91 1.29 A T =25°C 1.37 1.77 A 2.3V T =–40°Cto+85°C 1.37 1.77 A T =25°C 1.88 2.29 A 3V T =–40°Cto+85°C 1.88 2.29 A T =25°C 0.1 0.6 A 0.8V T =–40°Cto+85°C 0.1 0.6 A T =25°C 0.26 0.65 A 1.1V T =–40°Cto+85°C 0.26 0.65 A T =25°C 0.39 0.75 A VT– 1.4V Negative-going TA=–40°Cto+85°C 0.39 0.75 V inputthreshold T =25°C 0.47 0.84 A voltage 1.65V T =–40°Cto+85°C 0.47 0.84 A T =25°C 0.69 1.04 A 2.3V T =–40°Cto+85°C 0.69 1.04 A T =25°C 0.88 1.24 A 3V T =–40°Cto+85°C 0.88 1.24 A Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC T =25°C 0.07 0.5 A 0.8V T =–40°Cto+85°C 0.07 0.5 A T =25°C 0.08 0.46 A 1.1V T =–40°Cto+85°C 0.08 0.46 A T =25°C 0.18 0.56 A 1.4V ΔVT TA=–40°Cto+85°C 0.18 0.56 Hysteresis V (VT+–VT–) TA=25°C 1.65V 0.27 0.66 T =–40°Cto+85°C 0.27 0.66 A T =25°C 0.53 0.92 A 2.3V T =–40°Cto+85°C 0.53 0.92 A T =25°C 0.79 1.31 A 3V T =–40°Cto+85°C 0.79 1.31 A T =25°C V –0.1 A CC I =–20µA 0.8Vto3.6V OH T =–40°Cto+85°C V –0.1 A CC T =25°C 0.75×V A CC I =–1.1mA 1.1V OH T =–40°Cto+85°C 0.7×V A CC T =25°C 1.11 A I =–1.7mA 1.4V OH T =–40°Cto+85°C 1.03 A T =25°C 1.32 A I =–1.9mA 1.65V OH T =–40°Cto+85°C 1.3 A V V OH T =25°C 2.05 A I =–2.3mA OH T =–40°Cto+85°C 1.97 A 2.3V T =25°C 1.9 A I =–3.1mA OH T =–40°Cto+85°C 1.85 A T =25°C 2.72 A I =–2.7mA OH T =–40°Cto+85°C 2.67 A 3V T =25°C 2.6 A I =–4mA OH T =–40°Cto+85°C 2.55 A T =25°C 0.1 A I =20µA 0.8Vto3.6V OL T =–40°Cto+85°C 0.1 A 0.3× T =25°C A V CC I =1.1mA 1.1V OL 0.3× T =–40°Cto+85°C A V CC T =25°C 0.31 A I =1.7mA 1.4V OL T =–40°Cto+85°C 0.37 A T =25°C 0.31 A I =1.9mA 1.65V VOL OL TA=–40°Cto+85°C 0.35 V T =25°C 0.31 A I =2.3mA OL T =–40°Cto+85°C 0.33 A 2.3V T =25°C 0.44 A I =3.1mA OL T =–40°Cto+85°C 0.45 A T =25°C 0.31 A I =2.7mA OL T =–40°Cto+85°C 0.33 A 3V T =25°C 0.44 A I =4mA OL T =–40°Cto+85°C 0.45 A 6 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 Electrical Characteristics (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC T =25°C 0.1 A I Ainputs V =GNDto3.6V 0Vto3.6V µA I I T =–40°Cto+85°C 0.5 A T =25°C 0.2 A I V orV =0Vto3.6V 0V µA off I O T =–40°Cto+85°C 0.6 A T =25°C 0.2 A ΔI V orV =0Vto3.6V 0Vto0.2V µA off I O T =–40°Cto+85°C 0.6 A I VI=GNDor(VCCto3.6V), TA=25°C 0.8Vto3.6V 0.5 µA CC IO=0 TA=–40°Cto+85°C 0.9 T =25°C 40 A ΔI V =V 0.6V,I =0 3.3V µA CC I CC O T =–40°Cto+85°C 50 A 0V 1.5 C V =V orGND pF i I CC 3.6V 1.5 C V =GND 0V 2.5 pF o O 6.6 Switching Characteristics: C = 5 pF L overrecommendedoperatingfree-airtemperaturerange,C =5pF(unlessotherwisenoted)(seeFigure3andFigure4) L FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) V =0.8V T =25°C 22.7 CC A T =25°C 6.3 8 12.8 A VCC=1.2V±0.1V TA=–40°Cto 3.9 14.6 +85°C T =25°C 4.6 5.8 8.4 A VCC=1.5V±0.1V TA=–40°Cto 2.8 10 +85°C T =25°C 3.9 4.8 7.2 t A Y A ns pd VCC=1.8V±0.15V TA=–40°Cto 2.4 8.1 +85°C T =25°C 3.1 3.6 5.1 A VCC=2.5V±0.2V TA=–40°Cto 2 6.1 +85°C T =25°C 2.7 3 4.4 A VCC=3.3V±0.3V TA=–40°Cto 1.9 5.1 +85°C Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 6.7 Switching Characteristics: C = 10 pF L overrecommendedoperatingfree-airtemperaturerange,C =10pF(unlessotherwisenoted)(seeFigure3andFigure4) L FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) V =0.8V T =25°C 25.1 CC A T =25°C 7.1 9.1 13.8 A VCC=1.2V±0.1V TA=–40°Cto 4.7 15.6 +85°C T =25°C 5.2 6.5 9.4 A VCC=1.5V±0.1V TA=–40°Cto 3.4 11 +85°C T =25°C 4.5 5.4 8 t A Y A ns pd VCC=1.8V±0.15V TA=–40°Cto 2.9 9 +85°C T =25°C 3.5 4.2 5.7 A VCC=2.5V±0.2V TA=–40°Cto 2.4 6.8 +85°C T =25°C 3.1 3.5 4.9 A VCC=3.3V±0.3V TA=–40°Cto 2.2 5.7 +85°C 6.8 Switching Characteristics: C = 15 pF L overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure3andFigure4) L FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) V =0.8V T =25°C 27.6 CC A T =25°C 7.8 10.1 14.8 A VCC=1.2V±0.1V TA=–40°Cto 5.3 16.7 +85°C T =25°C 5.8 7.4 10.3 A VCC=1.5V±0.1V TA=–40°Cto 3.9 12 +85°C T =25°C 5 6.1 8.8 t A Y A ns pd VCC=1.8V±0.15V TA=–40°Cto 3.4 10 +85°C T =25°C 4 4.7 6.4 A VCC=2.5V±0.2V TA=–40°Cto 2.8 7.5 +85°C T =25°C 3.5 4.1 5.4 A VCC=3.3V±0.3V TA=–40°Cto 2.6 6.2 +85°C 8 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 6.9 Switching Characteristics: C = 30 pF L overrecommendedoperatingfree-airtemperaturerange,C =30pF(unlessotherwisenoted)(seeFigure3andFigure4) L FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) V =0.8V T =25°C 35.1 CC A T =25°C 10 13.1 18.1 A VCC=1.2V±0.1V TA=–40°Cto 7.5 19.8 +85°C T =25°C 7.4 9.6 12.9 A VCC=1.5V±0.1V TA=–40°Cto 5.6 14.9 +85°C T =25°C 6.4 7.9 11 t A Y A ns pd VCC=1.8V±0.15V TA=–40°Cto 4.8 12.4 +85°C T =25°C 5.2 6.1 7.9 A VCC=2.5V±0.2V TA=–40°Cto 4 9.3 +85°C T =25°C 4.6 5.3 6.7 A VCC=3.3V±0.3V TA=–40°Cto 3.6 7.7 +85°C 6.10 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS V TYP UNIT CC 0.8V 4 1.2V±0.1V 4 1.5V±0.1V 4 C Powerdissipationcapacitance f=10MHz pF pd 1.8V±0.15V 4 2.5V±0.2V 4.2 3.3V±0.3V 4.4 6.11 Typical Characteristics Static-Power Consumption Dynamic-Power Consumption Switching Characteristics (mA) (pF) at25MHz† 100% 100% 3.5 80% 80% 3 2.5 60% 3.3-V 60% 3.3-V −V 2 Input Output Logic† LLLoVVgCCic† ge 1.5 40% 40% olta 1 V 20% 20% 0.5 0% AAUUPP 0% AUP 0 † Single,dual,andtriplegates −0.50 5 10 15 20 25 30 35 40 45 Time−ns † AUP1G08dataatCL=15pF Figure1.AUP–TheLowest-PowerFamily Figure2.ExcellentSignalIntegrity Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 7 Parameter Measurement Information 7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration From Output Under Test CL 1 MW (see NoteA) LOAD CIRCUIT VCC= 0.8 V VC±C0=. 11 .V2 V VC±C0=. 11 .V5 V VC±C0=.1 15. 8V V VC±C0=. 22 .V5 V VC±C0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC tw VCC Input VCC/2 VCC/2 VI 0 V Input VM VM 0 V VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL Output VM VM VOH VCC VOL Timing Input VCC/2 0 V tPHL tPLH VOH tsu th Output VM VM VCC VOL Data Input VCC/2 VCC/2 0 V VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES VOLTAGE WAVEFORMS INVERTINGAND NONINVERTING OUTPUTS SETUPAND HOLD TIMES NOTES: A. CLincludes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50W, tr/tf= 3 ns. C. The outputs are measured one at a time, with one transition per measurement. D. tPLHand tPHLare the same as tpd. E. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitAndVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 7.2 Enable and Disable Times 2×VCC S1 5 kW From Output Under Test GND TEST S1 CL tPLZ/tPZL 2×VCC 5 kW (see NoteA) tPHZ/tPZH GND LOAD CIRCUIT VCC= 0.8 V VC±C0=. 11 .V2 V VC±C0=. 11 .V5 V VC±C0=.1 15. 8V V VC±C0=. 22 .V5 V VC±C0=. 33 .V3 V CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF VM VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VI VCC VCC VCC VCC VCC VCC VD 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCC Output Control VCC/2 VCC/2 0 V tPZL tPLZ Output Waveform 1 VCC S1 at 2×VCC VCC/2 VOL+ VD (see Note B) VOL tPZH tPHZ Output WSa1v eafto GrmN D2 VCC/2 VOH−VD VOH ≈0 V (see Note B) VOLTAGE WAVEFORMS ENABLEAND DISABLE TIMES LOW-AND HIGH-LEVELENABLING NOTES: A. CLincludes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50W, tr/tf= 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZand tPHZare the same as tdis. F. tPZLand tPZHare the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure4. LoadCircuitAndVoltageWaveforms Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 8 Detailed Description 8.1 Overview This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition andbetterswitching-noiseimmunityattheinput. The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of0.8Vto3.6V,resultinginanincreasedbatterylife. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs off off when the device is powered down. This inhibits current backflow into the device which prevents damage to the deviceandexcesspowerconsumption. 8.2 Functional Block Diagrams 2 4 A Y Figure5. LogicDiagram(PositiveLogic) (DBV,DCK,DPW,DRL,DRT,DRY,andYZPPackages) 1 3 A Y Figure6. LogicDiagram(PositiveLogic) (YFPPackage) 8.3 Feature Description 8.3.1 BalancedHigh-DriveCMOSPush-PullOutputs A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings table mustbefollowedatalltimes. 8.3.2 StandardCMOSInputs Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, givenintheElectricalCharacteristicstable,usingohm'slaw(R=V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions table to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device withaSchmitt-triggerinputshouldbeusedtoconditiontheinputsignalpriortothestandardCMOSinput. 12 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 Feature Description (continued) 8.3.3 ClampDiodes Theinputsandoutputstothisdevicehavenegativeclampingdiodes. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings maybeexceedediftheinputandoutputclamp-currentratingsareobserved. Device VCC Input Logic Output -IIK -IOK GND Figure7. ElectricalPlacementofClampingDiodesforEachInputandOutput 8.3.4 PartialPowerDown(I ) off The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by I in the Electrical off Characteristicstable. 8.3.5 Over-VoltageTolerantInputs Input signals to this device can be driven above the supply voltage so long as they remain below the maximum inputvoltagevaluespecifiedintheAbsoluteMaximumRatingstable. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSN74AUP1G17device. Table1.FunctionTable INPUT OUTPUT A Y H H L L Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information There are many situations in which a device needs to be initialized or held off for a short time at system turn-on. This application of the SN74AUP1G17 utilizes the delay created in an RC circuit to hold a line low for a short timewhenthesystemisfirststarted,thenmaintainsthelinehighwhilethesystemoperates.TheSN74AUP1G17 is ideal for this application because it must be tied directly to the primary supply for correct operation and is designedtodrawminimalsupplycurrentduringoperation. 9.2 Typical Application V CC V O V C Figure8. Turn-OnPulseGenerator(NormallyHighOutput) 9.2.1 DesignRequirements ThisdeviceusesCMOStechnologyandhasbalancedoutputdrive.Takecaretoavoidbuscontentionbecauseit can drive currents that would exceed maximum limits. The drive strength also creates fast edges into light loads, soroutingandloadconditionsshouldbeconsideredtopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions: – Forspecifiedhighandlowlevels,see(V andV )intheElectricalCharacteristicstable. T+ T- – Inputs are overvoltage tolerant allowing them to go as high as (V max) in the Absolute Maximum Ratings I tableatanyvalidV . CC 2. RecommendedOutputConditions: – Load currents should not exceed (I max) per output and should not exceed (continuous current through O V orGND)totalcurrentforthepart.TheselimitsarelocatedintheAbsoluteMaximumRatings table. CC 14 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 Typical Application (continued) 9.2.3 ApplicationCurve 100% 90% 80% )C 70% C of V 60% % 50% e ( g 40% a olt V 30% 20% VC 10% VCC VO 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Time (W) Figure9.SimulatedOutputResponsetoSupplyTurn-On Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 SCES579J–JUNE2004–REVISEDSEPTEMBER2017 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in the RecommendedOperatingConditionstable. Each V pin should have a good bypass capacitor to prevent power disturbance. It is ok to parallel multiple CC bypass caps to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. Thebypasscapacitormustbeinstalledasclosetothepowerpinaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 10 shows progressively better techniques of rounding corners. Only the lastexample(BEST)maintainsconstanttracewidthandminimizesreflections. An example layout is given in Figure 11 for the DPW (X2SON-5) package. This example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be usedtotraceoutthecenterpinconnectionthroughanotherboardlayer,oritcanbeleftoutofthelayout 11.2 Layout Example WORST BETTER BEST Figure10. TraceExample 0402 0.1 (cid:133)F Bypass Capacitor mil 4 8 mil 8 mil 8 mil SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP Figure11. ExampleLayoutWithDPW(X2SON-5)Package 16 SubmitDocumentationFeedback Copyright©2004–2017,TexasInstrumentsIncorporated ProductFolderLinks:SN74AUP1G17

SN74AUP1G17 www.ti.com SCES579J–JUNE2004–REVISEDSEPTEMBER2017 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • DesigningandManufacturingwithTI'sX2SONPackages • ImplicationsofSloworFloatingCMOSInputs • HowtoSelectLittleLogic • IntroductiontoLogic • SemiconductorPackingMaterialElectrostaticDischarge(ESD)Protection 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks NanoStar,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2004–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SN74AUP1G17

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74AUP1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (H175, H17F, H17K, & no Sb/Br) H17R) SN74AUP1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 H17F & no Sb/Br) SN74AUP1G17DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 H17F & no Sb/Br) SN74AUP1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (H175, H17F, H17K, & no Sb/Br) H17R) SN74AUP1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (H75, H7F, H7K, H7 & no Sb/Br) R) SN74AUP1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (H75, H7F, H7K, H7 & no Sb/Br) R) SN74AUP1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (H75, H7F, H7K, H7 & no Sb/Br) R) SN74AUP1G17DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C3 & no Sb/Br) SN74AUP1G17DRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (H77, H7R) & no Sb/Br) SN74AUP1G17DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 H7 & no Sb/Br) SN74AUP1G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 H7 & no Sb/Br) SN74AUP1G17YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM H7 & no Sb/Br) (2, N) SN74AUP1G17YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 H7N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AUP1G17 : •Enhanced Product: SN74AUP1G17-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUP1G17DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G17DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G17DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G17DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G17DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74AUP1G17DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74AUP1G17DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74AUP1G17DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74AUP1G17DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74AUP1G17DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3 SN74AUP1G17DRLR SOT-5X3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SN74AUP1G17DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AUP1G17DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74AUP1G17DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74AUP1G17DSFR SON DSF 6 5000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 SN74AUP1G17YFPR DSBGA YFP 4 3000 178.0 9.2 0.89 0.89 0.58 4.0 8.0 Q1 SN74AUP1G17YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUP1G17DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUP1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74AUP1G17DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74AUP1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74AUP1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AUP1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AUP1G17DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74AUP1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AUP1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AUP1G17DPWR X2SON DPW 5 3000 205.0 200.0 33.0 SN74AUP1G17DRLR SOT-5X3 DRL 5 4000 184.0 184.0 19.0 SN74AUP1G17DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0 SN74AUP1G17DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G17DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74AUP1G17DSFR SON DSF 6 5000 202.0 201.0 28.0 SN74AUP1G17YFPR DSBGA YFP 4 3000 220.0 220.0 35.0 SN74AUP1G17YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DPW0005A X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD B 0.85 A 0.75 PIN 1 INDEX AREA 0.85 0.75 0.4 MAX C SEATING PLANE NOTE 3 (0.1) 0.05 (0.25) 4X (0.05) 0.00 0.25 0.1 2 4 NOTE 3 2X 3 2X (0.26) 0.48 5 1 0.27 0.27 4X 0.17 0.17 0.1 C A B (0.06) 0.05 C 0.32 3X 0.23 4223102/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. www.ti.com

EXAMPLE BOARD LAYOUT DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM ( 0.1) 4X (0.42) VIA 0.05 MIN ALL AROUND 1 TYP 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP SOLDER MASK 4X (0.06) OPENING, TYP ( 0.25) (0.21) TYP METAL UNDER EXPOSED METAL SOLDER MASK CLEARANCE TYP LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X 4223102/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.06) 5 4X (0.22) 1 ( 0.24) 4X (0.26) SYMM (0.21) (0.48) TYP SOLDER MASK 3 EDGE 2 4 (R0.05) TYP SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0005 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP C SYMM 1 B D: Max = 1.418 mm, Min =1 .358 mm TYP 0.5 TYP E: Max = 0.918 mm, Min =0 .858 mm A 0.25 5X 1 2 0.21 0.015 C A B SYMM 4219492/A 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.23) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219492/A 05/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL SYMM TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219492/A 05/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

PACKAGE OUTLINE YFP0004 DSBGA - 0.5 mm max height SCALE 10.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.13 BALL TYP 0.05 C 0.4 TYP B D: Max = 0.79 mm, Min = 0.73 mm SYMM 0.4 E: Max = 0.79 mm, Min = 0.73 mm TYP A 0.25 4X 0.21 1 2 0.015 C A B SYMM 4223507/A 01/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YFP0004 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 4X ( 0.23) 1 2 A SYMM (0.4) TYP B SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:50X ( 0.23) 0.05 MAX 0.05 MIN METAL UNDER METAL SOLDER MASK EXPOSED SOLDER MASK EXPOSED ( 0.23) METAL OPENING METAL SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223507/A 01/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YFP0004 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 4X ( 0.25) (R0.05) TYP 1 2 A SYMM (0.4) TYP B METAL TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 4223507/A 01/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com

EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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