SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C–MAY2003–REVISEDJANUARY2007 FEATURES • AvailableintheTexasInstruments • LowPowerConsumption,10m Aat1.8V NanoFree™Package • – 8-mAOutputDriveat1.8V • Optimizedfor1.8-VOperationandIs3.6-VI/O • Latch-UpPerformanceExceeds100mAPer ToleranttoSupportMixed-ModeSignal JESD78,ClassII Operation • ESDProtectionExceedsJESD22 • I SupportsPartial-Power-DownMode off – 2000-VHuman-BodyModel(A114-A) Operation – 200-VMachineModel(A115-A) • Sub-1-VOperable – 1000-VCharged-DeviceModel(C101) • Maxt of1.2nsat1.8V pd DCT PACKAGE DCU PACKAGE YEPORYZPPACKAGE (TOPVIEW) (TOPVIEW) (BOTTOM VIEW) 1A 1 8 V 1A 1 8 VCC GND 45 2A CC 1B 2 7 1Y 2Y 36 2B 1B 27 1Y 1B 2 7 1Y 2Y 3 6 2B 1A 18 VCC GND 4 5 2A 2Y 3 6 2B GND 4 5 2A See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V CC to1.95-VV operation. CC TheSN74AUC2G00performstheBooleanfunctionY=A(cid:215) BorY=A+Binpositivelogic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING(2) A NanoFree™–WCSP(DSBGA) Reelof3000 SN74AUC2G00YZPR ___UA_ 0.23-mmLargeBump–YZP(Pb-free) –40°Cto85°C SSOP–DCT Reelof3000 SN74AUC2G00DCTR U00_ VSSOP–DCU Reelof3000 SN74AUC2G00DCUR U00_ (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. (2) DCT:Theactualtop-sidemarkinghasthreeadditionalcharactersthatdesignatetheyear,month,andassembly/testsite. DCU:Theactualtop-sidemarkinghasoneadditionalcharacterthatdesignatestheassembly/testsite. YZP:Theactualtop-sidemarkinghasthreeprecedingcharacterstodenoteyear,month,andsequencecode,andonefollowing charactertodesignatetheassembly/testsite. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. NanoFreeisatrademarkofTexasInstruments. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C–MAY2003–REVISEDJANUARY2007 FUNCTIONTABLE (EACHGATE) INPUTS OUTPUT A B Y H H L L X H X L H LOGICDIAGRAM(POSITIVELOGIC) 1 1A 7 2 1Y 1B 5 2A 3 6 2Y 2B Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 3.6 V CC V Inputvoltagerange(2) –0.5 3.6 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 3.6 V O V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent – 20 mA O ContinuouscurrentthroughV orGND – 100 mA CC DCTpackage 220 q Packagethermalimpedance(3) DCUpackage 227 (cid:176) C/W JA YZPpackage 102 T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. 2 SubmitDocumentationFeedback

SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C–MAY2003–REVISEDJANUARY2007 Recommended Operating Conditions(1) MIN MAX UNIT V Supplyvoltage 0.8 2.7 V CC V =0.8V V CC CC V High-levelinputvoltage V =1.1Vto1.95V 0.65×V V IH CC CC V =2.3Vto2.7V 1.7 CC V =0.8V 0 CC V Low-levelinputvoltage V =1.1Vto1.95V 0.35×V V IL CC CC V =2.3Vto2.7V 0.7 CC V Inputvoltage 0 3.6 V I V Outputvoltage 0 V V O CC V =0.8V –0.7 CC V =1.1V –3 CC I High-leveloutputcurrent V =1.4V –5 mA OH CC V =1.65V –8 CC V =2.3V –9 CC V =0.8V 0.7 CC V =1.1V 3 CC I Low-leveloutputcurrent V =1.4V 5 mA OL CC V =1.65V 8 CC V =2.3V 9 CC D t/D v Inputtransitionriseorfallrate 20 ns/V T Operatingfree-airtemperature –40 85 (cid:176) C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =–100m A 0.8Vto2.7V V –0.1 OH CC I =–0.7mA 0.8V 0.55 OH I =–3mA 1.1V 0.8 OH V V OH I =–5mA 1.4V 1 OH I =–8mA 1.65V 1.2 OH I =–9mA 2.3V 1.8 OH I =100m A 0.8Vto2.7V 0.2 OL I =0.7mA 0.8V 0.25 OL I =3mA 1.1V 0.3 OL V V OL I =5mA 1.4V 0.4 OL I =8mA 1.65V 0.45 OL I =9mA 2.3V 0.6 OL I AorBinputs V =V orGND 0to2.7V – 5 m A I I CC I V orV =2.7V 0 – 10 m A off I O I V =V orGND, I =0 0.8Vto2.7V 10 m A CC I CC O C V =V orGND 2.5V 2.5 pF i I CC (1) AlltypicalvaluesareatT =25°C. A SubmitDocumentationFeedback 3

SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C–MAY2003–REVISEDJANUARY2007 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure1) L V =1.2V V =1.5V V =1.8V V =2.5V PARAMETER FROM TO VCC=0.8V C–C0.1V C–C0.1V C– C0.15V C–C0.2V UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX t AorB Y 8 1 2.5 0.8 1.6 0.6 0.9 1.2 0.5 1 ns pd Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =30pF(unlessotherwisenoted)(seeFigure1) L V =1.8V V =2.5V CC CC PARAMETER FROM TO – 0.15V – 0.2V UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX t AorB Y 1.2 1.6 2.1 1 1.7 ns pd Operating Characteristics T =25°C A TEST VCC=0.8V VCC=1.2V VCC=1.5V VCC=1.8V VCC=2.5V PARAMETER UNIT CONDITIONS TYP TYP TYP TYP TYP Powerdissipation C f=10MHz 12 12 12 12 13 pF pd capacitance 4 SubmitDocumentationFeedback

SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C–MAY2003–REVISEDJANUARY2007 PARAMETER MEASUREMENT INFORMATION TEST S1 t /t Open PLH PHL 2 × VCC tPLZ/tPZL 2 × VCC R S1 Open tPHZ/tPZH GND From Output L Under Test GND (see NoteAC)L RL 0V.8C CV 15C pLF 2R kLW 0.V1D V 1.2 V±0.1 V 15 pF 2 kW 0.1 V 1.5 V±0.1 V 15 pF 2 kW 0.1 V LOAD CIRCUIT 1.8 V±0.15 V 15 pF 2 kW 0.15 V 2.5 V±0.2 V 15 pF 2 kW 0.15 V 1.8 V±0.15 V 30 pF 1 kW 0.15 V 2.5 V±0.2 V 30 pF 500W 0.15 V V CC Timing Input V /2 CC 0 V t W VCC tsu th V Input V /2 V /2 CC CC CC Data Input V /2 V /2 CC CC 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUPAND HOLD TIMES Input VCC/2 VCC/2 VCC COounttpruotl VCC/2 VCC/2 VCC 0 V 0 V t t t t PLH PHL PZL PLZ V Output V Output VCC/2 VCC/2 OH SW1a avte 2fo ×rm V 1 VCC/2 V + V CC VOL (see Note BCC) OL D VOL t t PHL PLH t t PZH PHZ Output VCC/2 VCC/2 VVOOHL (WseSae1v eNaOfoto utGretmpN Bu D2)t VCC/2 VOH–VD V»0OH V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR£10 MHz, Z = 50W, O slew rate³1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t and t are the same as t . PLZ PHZ dis F. t and t are the same as t . PZL PZH en G.t and t are the same as t . PLH PHL pd Figure1.LoadCircuitandVoltageWaveforms SubmitDocumentationFeedback 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AUC2G00DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 U00 & no Sb/Br) (R, Z) SN74AUC2G00DCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (U00Q, U00R) & no Sb/Br) UR SN74AUC2G00YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 UAN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUC2G00DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3 SN74AUC2G00DCUR VSSOP DCU 8 3000 178.0 9.5 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC2G00DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC2G00YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUC2G00DCTR SM8 DCT 8 3000 182.0 182.0 20.0 SN74AUC2G00DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 SN74AUC2G00DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 SN74AUC2G00YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DCT0008A SSOP - 1.3 mm max height SCALE 3.500 SMALL OUTLINE PACKAGE C 4.25 TYP 3.75 SEATING PLANE A PIN 1 ID AREA 0.1 C 6X 0.65 8 1 3.15 2X 2.75 1.95 NOTE 3 4 5 0.30 8X 0.15 2.9 0.13 C A B 1.3 B 2.7 1.0 NOTE 4 SEE DETAIL A (0.15) TYP 0.25 GAGE PLANE 0.1 0.6 0 - 8 0.0 0.2 DETAIL A TYPICAL 4220784/B 07/2020 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-187. www.ti.com

EXAMPLE BOARD LAYOUT DCT0008A SSOP - 1.3 mm max height SMALL OUTLINE PACKAGE 8X (1.1) SYMM (R0.05) 1 TYP 8 8X (0.4) SYMM 6X (0.65) 5 4 (3.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220784/B 07/2020 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DCT0008A SSOP - 1.3 mm max height SMALL OUTLINE PACKAGE 8X (1.1) SYMM 1 8 8X (0.4) SYMM 6X (0.65) 5 4 (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4220784/B 07/2020 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE YZP0008 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP D C SYMM 1.5 D: Max = 1.918 mm, Min =1 .858 mm TYP B E: Max = 0.918 mm, Min =0 .858 mm 0.5 TYP A 0.25 8X 1 2 0.21 0.015 C A B SYMM 4223082/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.23) 1 2 A (0.5) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223082/A 07/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL TYP D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4223082/A 07/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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