SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 FEATURES • AvailableintheTexasInstruments • LowPowerConsumption,10-μAMaxI CC NanoFree™Package • – 8-mAOutputDriveat1.8V • Optimizedfor1.8-VOperationandIs3.6-VI/O • Latch-UpPerformanceExceeds100mAPer ToleranttoSupportMixed-ModeSignal JESD78,ClassII Operation • ESDProtectionExceedsJESD22 • I SupportsPartial-Power-DownMode off – 2000-VHuman-BodyModel(A114-A) Operation – 200-VMachineModel(A115-A) • Sub-1-VOperable – 1000-VCharged-DeviceModel(C101) • Maxt of1.5nsat1.8V pd DCT PACKAGE DCU PACKAGE RSE PACKAGE YZP ORYZT PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) (BOTTOMVIEW) CLK 1 8 VCC CLK 1 8 VCC CLK D Q GNQD 3456 QCLR D 2 7 PRE D 27 PRE D 2 7 PRE Q 3 6 CLR 7 6 5 CLK 18 VCC Q 3 6 CLR GND 4 5 Q VCC 8 4 GND 1 2 3 GND 4 5 Q E R Q R L See mechanical drawings for dimensions. P C DESCRIPTION/ORDERING INFORMATION This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V , but is designed CC specificallyfor1.65-Vto1.95-VV operation. CC A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higherfrequencies,theCLRinputoverridesthePREinputwhentheyarebothlow. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. NanoFreeisatrademarkofTexasInstruments. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2003–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 ORDERINGINFORMATION T PACKAGE(1)(2) ORDERABLEPARTNUMBER TOP-SIDEMARKING(3) A NanoFree™–WCSP(DSBGA) Reelof3000 SN74AUC1G74YZPR 0.23-mmLargeBump–YZP(Pb-free) ___UP_ NanoFree™–WCSP(DSBGA) Reelof3000 SN74AUC1G74YZTR –40(cid:176) Cto85(cid:176) C 0.23-mmLargeBump–YZT(Pb-free) QFN–RSE Reelof3000 SN74AUC1G74RSER UP SSOP–DCT Reelof3000 SN74AUC1G74DCTR U74___ VSSOP–DCU Reelof3000 SN74AUC1G74DCUR U74_ (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. (2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (3) DCT:Theactualtop-sidemarkinghasthreeadditionalcharactersthatdesignatetheyear,month,andassembly/testsite. DCU:Theactualtop-sidemarkinghasoneadditionalcharacterthatdesignatestheassembly/testsite. YZP/YZT:Theactualtop-sidemarkinghasthreeprecedingcharacterstodenoteyear,month,andsequencecode,andonefollowing charactertodesignatetheassembly/testsite.Pin1identifierindicatessolder-bumpcomposition(1=SnPb,•=Pb-free). FUNCTIONTABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L X L X X L H H H › H H L H H › L L H H H L X Q Q 0 0 LOGICDIAGRAM(POSITIVELOGIC) 6 CLR CLK 1 C C C 3 Q TG 5 C C C Q C 2 D TG TG TG C C C 7 PRE A. PinnumbersshownarefortheDCT,DCU,YZP,andYZTpackagesonly. 2 SubmitDocumentationFeedback

SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 3.6 V CC V Inputvoltagerange(2) –0.5 3.6 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 3.6 V O V Outputvoltagerange(2) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent – 20 mA O ContinuouscurrentthroughV orGND – 100 mA CC DCTpackage 220 DCUpackage 227 θ Packagethermalimpedance(3) (cid:176) C/W JA RSEpackage 253 YZP/YZTpackage 102 T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. Recommended Operating Conditions(1) MIN MAX UNIT V Supplyvoltage 0.8 2.7 V CC V =0.8V V CC CC V High-levelinputvoltage V =1.1Vto1.95V 0.65· V V IH CC CC V =2.3Vto2.7V 1.7 CC V =0.8V 0 CC V Low-levelinputvoltage V =1.1Vto1.95V 0.35· V V IL CC CC V =2.3Vto2.7V 0.7 CC V Inputvoltage 0 3.6 V I V Outputvoltage 0 V V O CC V =0.8V –0.7 CC V =1.1V –3 CC I High-leveloutputcurrent V =1.4V –5 mA OH CC V =1.65V –8 CC V =2.3V –9 CC V =0.8V 0.7 CC V =1.1V 3 CC I Low-leveloutputcurrent V =1.4V 5 mA OL CC V =1.65V 8 CC V =2.3V 9 CC V =0.8Vto1.65V(2) 20 CC Δt/Δv Inputtransitionriseorfallrate V =1.65Vto2.3V(3) 20 ns/V CC V =2.3Vto2.7V(3) 20 CC T Operatingfree-airtemperature –40 85 (cid:176) C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. (2) ThedatawastakenatC =15pF,R =2kW (seeFigure1). L L (3) ThedatawastakenatC =30pF,R =500W (seeFigure1). L L SubmitDocumentationFeedback 3

SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =–100μA 0.8Vto2.7V V –0.1 OH CC I =–0.7mA 0.8V 0.55 OH I =–3mA 1.1V 0.8 OH V V OH I =–5mA 1.4V 1 OH I =–8mA 1.65V 1.2 OH I =–9mA 2.3V 1.8 OH I =100μA 0.8Vto2.7V 0.2 OL I =0.7mA 0.8V 0.25 OL I =3mA 1.1V 0.3 OL V V OL I =5mA 1.4V 0.4 OL I =8mA 1.65V 0.45 OL I =9mA 2.3V 0.6 OL I Allinputs V =V orGND 0to2.7V 5 μA I I CC I V orV =2.7V 0 – 10 μA off I O I V =V orGND, I =0 0.8Vto2.7V 10 μA CC I CC O C V =V orGND 2.5V 2.5 pF I I CC (1) AlltypicalvaluesareatT =25(cid:176) C. A Timing Requirements overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) V =1.2V V =1.5V V =1.8V V =2.5V VCC=0.8V C–C0.1V C–C0.1V C– C0.15V C–C0.2V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX f Clockfrequency 50 200 225 250 275 MHz clock CLK 2 1 1 1 1 tw Pulseduration PREorCLR ns 5 1.5 1 1 1 low Data 2.2 0.6 0.5 0.5 0.4 tsu SetuptimebeforeCLK› PREorCLR ns 2.9 1.6 0.9 0.7 0.4 inactive t Holdtime,dataafterCLK› 1.2 0.5 0.4 0.3 0.3 ns h Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure1) L V =1.2V V =1.5V V =1.8V V =2.5V PARAMETER FROM TO VCC=0.8V C–C0.1V C–C0.1V C– C0.15V C–C0.2V UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX f 50 200 225 250 275 MHz max Q 10.3 1.7 3.7 1.2 2.5 1 1.2 1.7 0.8 1.2 CLK t Q 9.6 1 3.8 1 3 0.9 1.1 1.5 0.7 1.1 ns pd PREorCLR QorQ 12.9 2 4.5 0.9 3.1 1.1 1.5 2.2 0.9 1.5 4 SubmitDocumentationFeedback

SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,C =30pF(unlessotherwisenoted)(seeFigure1) L V =1.8V V =2.5V CC CC PARAMETER FROM TO – 0.15V – 0.2V UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX f 250 275 ns max Q 1.5 1.9 2.4 1.4 1.8 CLK t Q 1.4 1.9 2.4 1.3 1.8 ns pd PREorCLR QorQ 1.7 2.2 2.8 1.5 2.1 Operating Characteristics T =25(cid:176) C A TEST VCC=0.8V VCC=1.2V VCC=1.5V VCC=1.8V VCC=2.5V PARAMETER UNIT CONDITIONS TYP TYP TYP TYP TYP Powerdissipation C f=10MHz 35 36 39 44 59 pF pd capacitance SubmitDocumentationFeedback 5

SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES537D–DECEMBER2003–REVISEDJUNE2007 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output RL S1 Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC CL tPHZ/tPZH GND (see Note A) RL VCC CL RL VD 0.8 V 15 pF 2 kW 0.1 V 1.2 V ± 0.1 V 15 pF 2 kW 0.1 V LOAD CIRCUIT 1.5 V ± 0.1 V 15 pF 2 kW 0.1 V 1.8 V ± 0.15 V 15 pF 2 kW 0.15 V 2.5 V ± 0.2 V 15 pF 2 kW 0.15 V 1.8 V ± 0.15 V 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V 30 pF 500 W 0.15 V VCC Timing Input VCC/2 0 V tw tsu th VCC VCC Input VCC/2 VCC/2 Data Input VCC/2 VCC/2 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC Output VCC Input VCC/2 VCC/2 Control VCC/2 VCC/2 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VCC Output VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + VD VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output Output VCC/2 VCC/2 VOH WSa1v eafto GrmN D2 VCC/2 VOH − VD VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms 6 SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AUC1G74DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 U74 & no Sb/Br) Z SN74AUC1G74DCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (74, U74Q, U74R) & no Sb/Br) UZ SN74AUC1G74DCURE4 ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 U74R & no Sb/Br) SN74AUC1G74DCURG4 ACTIVE VSSOP DCU 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 U74R & no Sb/Br) SN74AUC1G74RSER ACTIVE UQFN RSE 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UP & no Sb/Br) SN74AUC1G74YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 UPN & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUC1G74DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3 SN74AUC1G74DCUR VSSOP DCU 8 3000 180.0 9.0 2.05 3.3 1.0 4.0 8.0 Q3 SN74AUC1G74DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC1G74DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC1G74RSER UQFN RSE 8 3000 179.0 8.4 1.7 1.7 0.76 4.0 8.0 Q2 SN74AUC1G74YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jan-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUC1G74DCTR SM8 DCT 8 3000 182.0 182.0 20.0 SN74AUC1G74DCUR VSSOP DCU 8 3000 182.0 182.0 20.0 SN74AUC1G74DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 SN74AUC1G74DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0 SN74AUC1G74RSER UQFN RSE 8 3000 203.0 203.0 35.0 SN74AUC1G74YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE RSE0008A UQFN - 0.6 mm max height SCALE 7.000 PLASTIC QUAD FLATPACK - NO LEAD 1.55 B 1.45 A PIN 1 INDEX AREA 1.55 1.45 0.6 C 0.5 SEATING PLANE 0.05 0.00 0.05 C 0.35 2X 0.25 0.4 6X 0.3 0.1 C A B (0.12) 0.05 C 2X 0.45 TYP 0.35 4 3 5 2X SYMM 1 0.25 2X 0.15 7 1 0.1 C A B 4X 0.5 0.05 C 8 0.3 SYMM 4X 0.2 0.1 C A B PIN 1 ID 0.05 C (45 X 0.1) 4220323/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT RSE0008A UQFN - 0.6 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM (R0.05) TYP 2X (0.6) 8 6X (0.55) 1 7 4X (0.25) SYMM (1.3) 2X 4X (0.5) (0.2) 5 3 4 2X (0.3) (1.35) LAND PATTERN EXAMPLE SCALE:30X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL OPENING UNDER SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4220323/B 03/2018 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN RSE0008A UQFN - 0.6 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM (R0.05) TYP 2X (0.6) 8 6X (0.55) 1 7 4X (0.25) SYMM (1.3) 4X (0.5) 2X (0.2) 5 3 4 2X (0.3) (1.35) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICKNESS SCALE: 30X 4220323/B 03/2018 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0008 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP D C SYMM 1.5 D: Max = 1.919 mm, Min =1 .858 mm TYP B E: Max = 0.918 mm, Min =0 .857 mm 0.5 TYP A 0.25 8X 1 2 0.21 0.015 C A B SYMM 4223082/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.23) 1 2 A (0.5) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223082/A 07/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0008 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL TYP D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4223082/A 07/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,13 M 0,15 8 5 0,15 NOM 2,90 4,25 ÇÇÇÇÇ 2,70 3,75 ÇÇÇÇÇ ÇÇÇÇÇ Gage Plane ÇÇÇÇÇ PIN 1 INDEX AREA 0,25 1 4 0°– 8° 3,15 0,60 2,75 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 4188781/C 09/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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