SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 FEATURES DGV, DW, OR PW PACKAGE • OperatesFrom1.65Vto3.6V (TOP VIEW) • Maxt of3.3nsat3.3V pd • – 24-mAOutputDriveat3.3V OE 1 20 VCC • BusHoldonDataInputsEliminatestheNeed 1Q 2 19 8Q 1D 3 18 8D forExternalPullup/PulldownResistors 2D 4 17 7D • Latch-UpPerformanceExceeds100mAPer 2Q 5 16 7Q JESD78,ClassII 3Q 6 15 6Q • ESDProtectionExceedsJESD22 3D 7 14 6D – 2000-VHuman-BodyModel(A114-A) 4D 8 13 5D – 200-VMachineModel(A115-A) 4Q 9 12 5Q GND 10 11 LE – 1000-VCharged-DeviceModel(C101) DESCRIPTION/ORDERING INFORMATION ThisoctaltransparentD-typelatchisdesignedfor1.65-Vto3.6-VV operation. CC The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LEistakenlow,theQoutputsarelatchedatthelogiclevelssetupattheDinputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines withoutinterfaceorpullupcomponents. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered whiletheoutputsareinthehigh-impedancestate. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Activebus-holdcircuitryholdsunusedorundriveninputsata valid logic state. Use of pullup or pulldown resistors withthebus-holdcircuitryisnotrecommended. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A Tube SN74ALVCH373DW SOIC-DW ALVCH373 Tapeandreel SN74ALVCH373DWR TSSOP-PW Tapeandreel SN74ALVCH373PWR VB373 -40(cid:176) Cto85(cid:176) C TVSOP-DGV Tapeandreel SN74ALVCH373DGVR VB373 VFBGA-GQN SN74ALVCH373GQNR Tapeandreel VB373 VFBGA-ZQN(Pb-free) SN74ALVCH373ZQNR (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1997–2004,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 GQN OR ZQN PACKAGE TERMINALASSIGNMENTS (TOP VIEW) 1 2 3 4 1 2 3 4 A 1Q OE V 8Q CC B 2D 7D 1D 8D A C 3Q 2Q 6Q 7Q B D 4D 5D 3D 6D C E GND 4Q LE 5Q D E FUNCTIONTABLE (eachlatch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z LOGICDIAGRAM(POSITIVELOGIC) 1 OE 11 LE C1 2 3 1Q 1D 1D To Seven Other Channels Pin numbers shown are for the DGV, DW, and PW packages. 2

SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange -0.5 4.6 V CC V Inputvoltagerange(2) -0.5 4.6 V I V Outputvoltagerange(2)(3) -0.5 V +0.5 V O CC I Inputclampcurrent V <0 -50 mA IK I I Outputclampcurrent V <0 -50 mA OK O I Continuousoutputcurrent – 50 mA O ContinuouscurrentthroughV orGND – 100 mA CC DGVpackage 92 DWpackage 58 q Packagethermalimpedance(4) (cid:176) C/W JA GQN/ZQNpackage 78 PWpackage 83 T Storagetemperaturerange -65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto4.6Vmaximum. (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. RECOMMENDED OPERATING CONDITIONS(1) MIN MAX UNIT V Supplyvoltage 1.65 3.6 V CC V =1.65Vto1.95V 0.65· V CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V IH CC V =2.7Vto3.6V 2 CC V =1.65Vto1.95V 0.35· V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0.7 V IL CC V =2.7Vto3.6V 0.8 CC V Inputvoltage 0 V V I CC V Outputvoltage 0 V V O CC V =1.65V -4 CC V =2.3V -12 CC I High-leveloutputcurrent mA OH V =2.7V -12 CC V =3V -24 CC V =1.65V 4 CC V =2.3V 12 CC I Low-leveloutputcurrent mA OL V =2.7V 12 CC V =3V 24 CC D t/D v Inputtransitionriseorfallrate 5 ns/V T Operatingfree-airtemperature -40 85 (cid:176) C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 3

SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 ELECTRICAL CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =-100m A 1.65Vto3.6V V -0.2 OH CC I =-4mA 1.65V 1.2 OH I =-6mA 2.3V 2 OH V 2.3V 1.7 V OH I =-12mA 2.7V 2.2 OH 3V 2.4 I =-24mA 3V 2 OH I =100m A 1.65Vto3.6V 0.2 OL I =4mA 1.65V 0.45 OL I =6mA 2.3V 0.4 OL V V OL 2.3V 0.7 I =12mA OL 2.7V 0.4 I =24mA 3V 0.55 OL I V =V orGND 3.6V – 5 m A I I CC V =0.58V 1.65V 25 I V =1.07V 1.65V -25 I V =0.7V 2.3V 45 I I V =1.7V 2.3V -45 m A I(hold) I V =0.8V 3V 75 I V =2V 3V -75 I V =0to3.6V(2) 3.6V – 500 I I V =V orGND 3.6V – 10 m A OZ O CC I V =V orGND, I =0 3.6V 20 m A CC I CC O D I OneinputatV -0.6V, OtherinputsatV orGND 3Vto3.6V 750 m A CC CC CC Controlinputs 4.5 C V =V orGND 3.3V pF i I CC Datainputs 5 C Outputs V =V orGND 3.3V 7.5 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25(cid:176) C. CC A (2) Thisisthebus-holdmaximumdynamiccurrent.Itistheminimumoverdrivecurrentrequiredtoswitchtheinputfromonestateto another. TIMING REQUIREMENTS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) V =2.5V V =3.3V VCC=1.8V C–C0.2V VCC=2.7V C–C0.3V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhigh 3.8 3.3 3.3 3.3 ns w t Setuptime,databeforeLEfl 1.3 0.5 0.5 0.5 ns su t Holdtime,dataafterLEfl 0.5 1.3 1.7 1.2 ns h 4

SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C– C0.15V C–C0.2V VCC=2.7V C–C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX D 1.7 6.3 1 4 4 1 3.6 t Q ns pd LE 2 6.1 1 3.8 3.7 1 3.3 t OE Q 3.4 8.3 1.9 5.4 5.4 1.6 4.8 ns en t OE Q 1.6 7 1 4.4 4.4 1 4.4 ns dis OPERATING CHARACTERISTICS T =25(cid:176) C A TEST VCC=1.8V VCC=2.5V VCC=3.3V PARAMETER UNIT CONDITIONS TYP TYP TYP Powerdissipation Outputsenabled 31 33 37 C C =0,f=10MHz pF pd capacitanceperlatch Outputsdisabled L 7 7 9 5

SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H–JULY1997–REVISEDOCTOBER2004 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tpd Open (see Note CAL) RL ttPPHLZZ//ttPPZZLH VGLNOADD LOAD CIRCUIT INPUT VCC VM VLOAD CL RL VD VI tr/tf 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V tw VI Timing VI Input VM VM Input VM 0 V 0 V VOLTAGE WAVEFORMS PULSE DURATION tsu th IDnpautat VM VM VI COounttpruotl VI 0 V (low-level VM VM enabling) 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPZL tPLZ Output VI Waveform 1 VLOAD/2 Input VM VM S1 at VLOAD VM VOL + VD 0 V (see Note B) VOL tPLH tPHL tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VD VOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74ALVCH373DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VB373 & no Sb/Br) SN74ALVCH373DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH373 & no Sb/Br) SN74ALVCH373DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH373 & no Sb/Br) SN74ALVCH373PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VB373 & no Sb/Br) SN74ALVCH373PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 VB373 & no Sb/Br) SN74ALVCH373ZQNR LIFEBUY BGA ZQN 20 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 VB373 MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALVCH373DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74ALVCH373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ALVCH373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74ALVCH373ZQNR BGAMI ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALVCH373DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74ALVCH373DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALVCH373PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74ALVCH373ZQNR BGAMICROSTAR ZQN 20 1000 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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