SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 FEATURES DGG OR DL PACKAGE • MemberoftheTexasInstrumentsWidebus™ (TOP VIEW) Family • BusHoldonDataInputsEliminatestheNeed 1OE 1 48 1LE forExternalPullup/PulldownResistors 1Q1 2 47 1D1 • OutputPortsHaveEquivalent26-W Series 1Q2 3 46 1D2 Resistors,SoNoExternalResistorsAre GND 4 45 GND Required 1Q3 5 44 1D3 • Latch-UpPerformanceExceeds250mAPer 1Q4 6 43 1D4 V 7 42 V JESD17 CC CC 1Q5 8 41 1D5 • ESDProtectionExceedsJESD22 1Q6 9 40 1D6 – 2000-VHuman-BodyModel(A114-A) GND 10 39 GND – 200-VMachineModel(A115-A) 1Q7 11 38 1D7 1Q8 12 37 1D8 DESCRIPTION/ORDERING INFORMATION 2Q1 13 36 2D1 2Q2 14 35 2D2 This 16-bit transparent D-type latch is designed for 1.65-Vto3.6-VV operation. GND 15 34 GND CC 2Q3 16 33 2D3 The SN74ALVCH162373 is particularly suitable for 2Q4 17 32 2D4 implementing buffer registers, I/O ports, bidirectional V 18 31 V bus drivers, and working registers. This device can CC CC 2Q5 19 30 2D5 be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q 2Q6 20 29 2D6 outputs follow the data (D) inputs. When LE is taken GND 21 28 GND low, the Q outputs are latched at the levels set up at 2Q7 22 27 2D7 theDinputs. 2Q8 23 26 2D8 2OE 24 25 2LE A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputsareinthehigh-impedancestate. The outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and undershoot. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A Tube SN74ALVCH162373DL SSOP-DL ALVCH162373 Tapeandreel SN74ALVCH162373LR -40(cid:176) Cto85(cid:176) C TSSOP-DGG Tapeandreel SN74ALVCH162373GR ALVCH162373 VFBGA-GQL Tapeandreel SN74ALVCH162373KR VH2373 (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. WidebusisatrademarkofTexasInstruments. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2004,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistorswiththebus-holdcircuitryisnotrecommended. XXX GQL PACKAGE XXX (TOP VIEW) TERMINALASSIGNMENTS(1) 1 2 3 4 5 6 1 2 3 4 5 6 A 1OE NC NC NC NC 1LE A B 1Q2 1Q1 GND GND 1D1 1D2 B C 1Q4 1Q3 V V 1D3 1D4 CC CC C D 1Q6 1Q5 GND GND 1D5 1D6 D E 1Q8 1Q7 1D7 1D8 E F 2Q1 2Q2 2D2 2D1 F G 2Q3 2Q4 GND GND 2D4 2D3 G H 2Q5 2Q6 V V 2D6 2D5 CC CC H J 2Q7 2Q8 GND GND 2D8 2D7 J K 2OE NC NC NC NC 2LE K (1) NC-Nointernalconnection FUNCTIONTABLE (each8-bitsection) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q 0 H X X Z LOGICDIAGRAM(POSITIVELOGIC) 1 24 1OE 2OE 48 25 1LE 2LE C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG and DL packages. 2

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange -0.5 4.6 V CC V Inputvoltagerange(2) -0.5 4.6 V I V Outputvoltagerange(2)(3) -0.5 V +0.5 V O CC I Inputclampcurrent V <0 -50 mA IK I I Outputclampcurrent V <0 -50 mA OK O I Continuousoutputcurrent – 50 mA O ContinuouscurrentthrougheachV orGND – 100 mA CC DGGpackage 70 q Packagethermalimpedance(4) DLpackage 63 (cid:176) C/W JA GQLpackage 42 T Storagetemperaturerange -65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto4.6Vmaximum. (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. RECOMMENDED OPERATING CONDITIONS(1) MIN MAX UNIT V Supplyvoltage 1.65 3.6 V CC V =1.65Vto1.95V 0.65· V V CC CC CC V High-levelinputvoltage V =2.3Vto2.7V 1.7 V V IH CC CC V =2.7Vto3.6V 2 V CC CC V =1.65Vto1.95V 0 0.35· V CC CC V Low-levelinputvoltage V =2.3Vto2.7V 0 0.7 V IL CC V =2.7Vto3.6V 0 0.8 CC V Outputvoltage 0 V V O CC V =1.65V -2 CC V =2.3V -6 CC I High-leveloutputcurrent mA OH V =2.7V -8 CC V =3V -12 CC V =1.65V 2 CC V =2.3V 6 CC I Low-leveloutputcurrent mA OL V =2.7V 8 CC V =3V 12 CC D t/D v Inputtransitionriseorfallrate 10 ns/V T Operatingfree-airtemperature -40 85 (cid:176) C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 3

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 ELECTRICAL CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP(1) MAX UNIT CC I =-100m A 1.65Vto3.6V V -0.2 OH CC I =-2mA 1.65V 1.2 OH I =-4mA 2.3V 1.9 OH V 2.3V 1.7 V OH I =-6mA OH 3V 2.4 I =-8mA 2.7V 2 OH I =-12mA 3V 2 OH I =100m A 1.65Vto3.6V 0.2 OL I =2mA 1.65V 0.45 OL I =4mA 2.3V 0.4 OL V 2.3V 0.55 V OL I =6mA OL 3V 0.55 I =8mA 2.7V 0.6 OL I =12mA 3V 0.8 OL I V =V orGND 3.6V – 5 m A I I CC V =0.58V 1.65V 25 I V =1.07V 1.65V -25 I V =0.7V 2.3V 45 I I V =1.7V 2.3V -45 m A I(hold) I V =0.8V 3V 75 I V =2V 3V -75 I V =0to3.6V(2) 3.6V – 500 I I V =V orGND 3.6V – 10 m A OZ O CC I V =V orGND, I =0 3.6V 40 m A CC I CC O D I OneinputatV -0.6V, OtherinputsatV orGND 3Vto3.6V 750 m A CC CC CC Controlinputs 3 C V =V orGND 3.3V pF i I CC Datainputs 6 C Outputs V =V orGND 3.3V 7 pF o O CC (1) AlltypicalvaluesareatV =3.3V,T =25(cid:176) C. CC A (2) Thisisthebus-holdmaximumdynamiccurrent.Itistheminimumoverdrivecurrentrequiredtoswitchtheinputfromonestateto another. TIMING REQUIREMENTS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) V =1.8V V =2.5V V =3.3V C– C0.15V C–C0.2V VCC=2.7V C–C0.3V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t Pulseduration,LEhighorlow 3.3 3.3 3.3 3.3 ns w t Setuptime,databeforeLEfl 1.1 1.1 1.1 1.1 ns su t Holdtime,dataafterLEfl 1.1 1.1 1.1 1.1 ns h 4

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 SWITCHING CHARACTERISTICS overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure1) V =1.8V V =2.5V V =3.3V PARAMETER FROM TO C– C0.15V C–C0.2V VCC=2.7V C–C0.3V UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX D 1 6.3 1 5.3 1 4.5 1.1 4 t Q ns pd LE 1 6.6 1 5.6 1 5 1 4.2 t OE Q 1 7.2 1 6.5 1.5 6 1 5 ns en t OE Q 1 6.5 1 5.6 1.5 5.5 1.4 4.5 ns dis t 1 0.5 0.5 0.5 ns sk(o) OPERATING CHARACTERISTICS T =25(cid:176) C A V =1.8V V =2.5V V =3.3V CC CC CC PARAMETER TESTCONDITIONS UNIT TYP TYP TYP Outputsenabled 20 22 26 C Powerdissipationcapacitance C =50pF, f=10MHz pF pd L Outputsdisabled 6 6.5 8 5

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A–JULY2004–REVISEDOCTOBER2004 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tpd Open (see Note CAL) RL ttPPHLZZ//ttPPZZLH VGLNOADD LOAD CIRCUIT INPUT VCC VM VLOAD CL RL VD VI tr/tf 1.8 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 W 0.3 V tw VI Timing VI Input VM VM Input VM 0 V 0 V VOLTAGE WAVEFORMS PULSE DURATION tsu th IDnpautat VM VM VI COounttpruotl VI 0 V (low-level VM VM enabling) 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPZL tPLZ Output VI Waveform 1 VLOAD/2 Input VM VM S1 at VLOAD VM VOL + VD 0 V (see Note B) VOL tPLH tPHL tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VD VOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74ALVCH162373DLG4 ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 & no Sb/Br) 74ALVCH162373ZQLR LIFEBUY BGA ZQL 56 1000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 VH2373 MICROSTAR & no Sb/Br) JUNIOR SN74ALVCH162373DL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 & no Sb/Br) SN74ALVCH162373GR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 & no Sb/Br) SN74ALVCH162373LR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74ALVCH162373ZQLR BGAMI ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 CROSTA RJUNI OR SN74ALVCH162373GR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74ALVCH162373LR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74ALVCH162373ZQLR BGAMICROSTAR ZQL 56 1000 350.0 350.0 43.0 JUNIOR SN74ALVCH162373GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVCH162373LR SSOP DL 48 1000 367.0 367.0 55.0 PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OUTLINE ZQL0056A JRBGA - 1 mm max height SCALE 2.100 PLASTIC BALL GRID ARRAY 4.6 B A 4.4 BALL A1 CORNER 7.1 6.9 1 MAX C SEATING PLANE 0.35 0.15 TYP BALL TYP 0.1 C 3.25 TYP SYMM (0.625) TYP K J (0.575) TYP H G 5.85 F SYMM TYP E D C 0.45 56X NOTE 3 0.35 B 0.15 C B A 0.08 C A 0.65 TYP 1 2 3 4 5 6 BALL A1 CORNER 0.65 TYP 4219711/B 01/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. No metal in this area, indicates orientation. www.ti.com

EXAMPLE BOARD LAYOUT ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY (0.65) TYP 56X ( 0.33) 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK 0.05 MAX 0.05 MIN METAL UNDER OPENING SOLDER MASK EXPOSED METAL ( 0.33) ( 0.33) METAL EXPOSED METAL SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219711/B 01/2017 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com

EXAMPLE STENCIL DESIGN ZQL0056A JRBGA - 1 mm max height PLASTIC BALL GRID ARRAY 56X ( 0.33) (0.65) TYP 1 2 3 4 5 6 A (0.65) TYP B C D E SYMM F G H J K SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4219711/B 01/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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