SN74ALVC00-Q1 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES490C − SEPTEMBER 2003 − REVISED JANUARY 2008 (cid:2) Qualified for Automotive Applications D OR PW PACKAGE (cid:2) (TOP VIEW) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V 1A 1 14 V Using Machine Model (C = 200 pF, R = 0) CC (cid:2) 1B 2 13 4B Operates From 1.65 V to 3.6 V 1Y 3 12 4A (cid:2) Max t of 3 ns at 3.3 V pd 2A 4 11 4Y (cid:2) ±24-mA Output Drive at 3.3 V 2B 5 10 3B (cid:2) Latch-Up Performance Exceeds 250 mA Per 2Y 6 9 3A JESD 17 GND 7 8 3Y description/ordering informatiom The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V operation. CC The device performs the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION† ORDERABLE TOP-SIDE TA PACKAGE‡ PART NUMBER MARKING SOIC − D Tape and reel SN74ALVC00IDRQ1 ALVC00I −4400°°CC ttoo 8855°°CC TSSOP − PW Tape and reel SN74ALVC00IPWRQ1 VA00I †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE (each gate) INPUTS OOUUTTPPUUTT A B Y H H L L X H X L H logic diagram, each gate (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN74ALVC00-Q1 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES490C − SEPTEMBER 2003 − REVISED JANUARY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V I Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W JA PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 1.65 3.6 V VCC = 1.65 V to 1.95 V 0.65 ×VCC VVIIHH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 2.3 V to 2.7 V 1.7 VV VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 ×VCC VVIILL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 2.3 V to 2.7 V 0.7 VV VCC = 2.7 V to 3.6 V 0.8 VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 1.65 V −4 VCC = 2.3 V −12 IIOH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 2.7 V −12 mmAA VCC = 3 V −24 VCC = 1.65 V 4 VCC = 2.3 V 12 IIOL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 2.7 V 12 mmAA VCC = 3 V 24 Δt/Δv Input transition rise or fall rate 5 ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ALVC00-Q1 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES490C − SEPTEMBER 2003 − REVISED JANUARY 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT IOH = −100 μA 1.65 V to 3.6 V VCC−0.2 IOH = −4 mA 1.65 V 1.2 IOH = −6 mA 2.3 V 2 VVOOHH 2.3 V 1.7 VV IIOOHH = −1122 mmAA 2.7 V 2.2 3 V 2.4 IOH = −24 mA 3 V 2 IOL = 100 μA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 VVOL 2.3 V 0.7 VV IIOL = 1122 mmAA 2.7 V 0.4 IOL = 24 mA 3 V 0.55 II VI = VCC or GND 3.6 V ±5 μA ICC VI = VCC or GND, IO = 0 3.6 V 10 μA ΔICC One input at VCC − 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 μA Ci VI = VCC or GND 3.3 V 4.5 pF †All typical values are at VCC = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PPAARRAAMMEETTEERR FROM TO VC±C 0 =.1 15. 8V V VC±C 0=. 22 .V5 V VCC = 2.7 V VC±C 0=. 33 .V3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX MIN MAX MIN MAX tpd A or B Y 1 4.4 1 2.8 3.2 0.5 3 ns operating characteristics, TA = 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT TYP TYP TYP Cpd Power dissipation capacitance per gate CL = 0, f = 10 MHz 20 21 23 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN74ALVC00-Q1 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES490C − SEPTEMBER 2003 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION VLOAD From Output RL S1 Open TEST S1 Under Test GND tpd Open (see Note CAL) RL ttPPHLZZ//ttPPZZLH VGLNOADD LOAD CIRCUIT INPUT VCC VM VLOAD CL RL VΔ VI tr/tf 1.8 V ±0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V 2.5 ±0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V 3.3 V ±0.3 V 2.7 V ≤2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V tw VI Timing VI Input VM VM Input VM 0 V 0 V VOLTAGE WAVEFORMS PULSE DURATION tsu th IDnpautat VM VM VI COounttpruotl VI 0 V (low-level VM VM enabling) 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPZL tPLZ Output VI Waveform 1 VLOAD/2 Input VM VM S1 at VLOAD VM VOL + VΔ 0 V (see Note B) VOL tPLH tPHL tPZH tPHZ Output VM VM VOH WSa1v eaOfto uGrtmpNu D2t VM VOH − VΔ VOH VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74ALVC00IPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC00I & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74ALVC00-Q1 : Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: SN74ALVC00 •Enhanced Product: SN74ALVC00-EP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALVC00IPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALVC00IPWRG4Q1 TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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