(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 • Package Options Include Plastic SN54ALS74A, SN54AS74A...J PACKAGE Small-Outline (D) Packages, Ceramic Chip SN74ALS74A, SN74AS74A...D OR N PACKAGE (TOP VIEW) Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1CLR 1 14 VCC 1D 2 13 2CLR TYPICAL MAXIMUM TYPICAL POWER 1CLK 3 12 2D CLOCK FREQUENCY DISSIPATION TYPE (CL = 50 pF) PER FLIP-FLOP 1PRE 4 11 2CLK (MHz) (mW) 1Q 5 10 2PRE ′ALS74A 50 6 1Q 6 9 2Q ′AS74A 134 26 GND 7 8 2Q description SN54ALS74A, SN54AS74A...FK PACKAGE (TOP VIEW) These devices contain two independent R R positive-edge-triggered D-type flip-flops. A low L CL D C C CC level at the preset (PRE) or clear (CLR) inputs sets 1 1 N V 2 or resets the outputs regardless of the levels of the 3 2 1 20 19 other inputs. When PRE and CLR are inactive 1CLK 4 18 2D (high), data at the data (D) input meeting the NC 5 17 NC setup-time requirements are transferred to the 1PRE 6 16 2CLK outputs on the positive-going edge of the clock NC 7 15 NC (CLK) pulse. Clock triggering occurs at a voltage 1Q 8 14 2PRE level and is not directly related to the rise time of 9 10 11 12 13 CLK. Following the hold-time interval, data at the Q DC QQ D input can be changed without affecting the 1 NN 22 G levels at the outputs. NC − No internal connection The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 †The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. (cid:12)(cid:20)(cid:13)(cid:10)(cid:11)(cid:25)(cid:15)(cid:14)(cid:13)(cid:2) (cid:10)(cid:5)(cid:15)(cid:5) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  1995, Texas Instruments Incorporated (cid:12)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:15)&-!# (cid:14)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:12)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 logic symbol† 4 1PRE S 5 1Q 3 1CLK C1 2 1D 1D 6 1 1Q 1CLR R 10 2PRE 9 2Q 11 2CLK 12 2D 8 13 2Q 2CLR †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) PRE CLR Q Q CLK D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Operating free-air temperature range, T : SN54ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C A SN74ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 recommended operating conditions SN54ALS74A SN74ALS74A UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA fclock Clock frequency 0 25 0 34 MHz PRE or CLR low 15 15 ttww PPuullssee dduurraattiioonn CLK high 17.5 14.5 nnss CLK low 17.5 14.5 Data 16 15 ttssuu SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss PRE or CLR inactive 10 10 th Hold time after CLK↑ Data 2 0 ns TA Operating free-air temperature −55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ALS74A SN74ALS74A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V VOH VCC = 4.5 V to 5.5 V, IOH = −2 mA VCC−2 VCC−2 V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44..55 VV VV IOL = 8 mA 0.35 0.5 CLK or D 0.1 0.1 IIII VVCCCC == 44..55 VV,, VVII == 77 VV mmAA PRE or CLR 0.2 0.2 CLK or D 20 20 IIIIHH VVCCCC == 44..55 VV,, VVII == 22..77 VV µAA PRE or CLR 40 40 CLK or D −0.2 −0.2 IIIILL VVCCCC == 44..55 VV,, VVII == 00..44 VV mmAA PRE or CLR −0.4 −0.4 IO‡ VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 3 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, FROM TO RL = 500 Ω, PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX† UUNNIITT SN54ALS74A SN74ALS74A MIN MAX MIN MAX fmax 25 34 MHz tPLH 3 18 3 13 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 5 17 5 15 tPLH 5 23 5 16 CCLLKK QQ oorr QQ nnss tPHL 5 20 5 18 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Operating free-air temperature range, T : SN54AS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C A SN74AS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS74A SN74AS74A UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −2 −2 mA IOL Low-level output current 20 20 mA fclock* Clock frequency 0 90 0 105 MHz PRE or CLR low 4 4 ttww** PPuullssee dduurraattiioonn CLK high 4 4 nnss CLK low 5.5 5.5 Data 4.5 4.5 ttssuu** SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss PRE or CLR inactive 2 2 th* Hold time after CLK↑ Data 0 0 ns TA Operating free-air temperature −55 125 0 70 °C * On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested. 4 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54AS74A SN74AS74A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V VOH VCC = 4.5 V to 5.5 V, IOH = −2 mA VCC−2 VCC−2 V VOL VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA CLK or D 20 20 IIIIHH VVCCCC == 55..55 VV,, VVII == 22..77 VV µAA PRE or CLR 40 40 CLK or D −0.5 −0.5 IIIILL VVCCCC == 55..55 VV,, VVII == 00..44 VV mmAA PRE or CLR −1.8 −1.8 IO‡ VCC = 5.5 V, VO = 2.25 V −30 −112 −30 −112 mA ICC VCC = 5.5 V, See Note 1 10.5 16 10.5 16 mA †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded. switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, FROM TO RL = 500 Ω, PPAARRAAMMEETTEERR ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX§ UUNNIITT SN54AS74A SN74AS74A MIN MAX MIN MAX fmax* 90 105 MHz tPLH 2 9 2 7.5 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 2.5 11.5 2.5 10.5 tPLH 2.5 10 3 8 CCLLKK QQ oorr QQ nnss tPHL 3.5 10.5 3 9 * On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested. §For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 5 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:6)(cid:1)(cid:7)(cid:4)(cid:5)(cid:8)(cid:9)(cid:1)(cid:2)(cid:7)(cid:4)(cid:5)(cid:1)(cid:7)(cid:4)(cid:5) (cid:10)(cid:11)(cid:5)(cid:6)(cid:9)(cid:12)(cid:13)(cid:1)(cid:14)(cid:15)(cid:14)(cid:16)(cid:17)(cid:18)(cid:17)(cid:10)(cid:19)(cid:17)(cid:18)(cid:15)(cid:20)(cid:14)(cid:19)(cid:19)(cid:17)(cid:20)(cid:17)(cid:10)(cid:9)(cid:10)(cid:18)(cid:15)(cid:21)(cid:12)(cid:17)(cid:9)(cid:22)(cid:6)(cid:14)(cid:12)(cid:18)(cid:22)(cid:6)(cid:13)(cid:12)(cid:1) (cid:23)(cid:14)(cid:15)(cid:24)(cid:9)(cid:25)(cid:6)(cid:17)(cid:5)(cid:20)(cid:9)(cid:5)(cid:2)(cid:10)(cid:9)(cid:12)(cid:20)(cid:17)(cid:1)(cid:17)(cid:15) SDAS143C − APRIL 1982 − REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC RL = R1 = R2 S1 RL R1 From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point (see Note CAL) RL CL (see Note CAL) R2 (see Note A) LOAD CIRCUIT FOR BI-STATE LOAD CIRCUIT LOAD CIRCUIT TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3.5 V 3.5 V Timing High-Level Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level Input 1.3 V 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output Control 1.3 V 1.3 V (low-level enabling) 0.3 V 3.5 V tPZL Input 1.3 V 1.3 V tPLZ 0.3 V (cid:1)3.5 V Waveform 1 tPLH tPHL S1 Closed 1.3 V In-Phase VOH (see Note B) VOL Output 1.3 V 1.3 V tPHZ 0.3 V VOL tPZH tPLH VOH tPHL Waveform 2 Out-of-Phase VOH S1 Open 1.3 V 0.3 V Output 1.3 V 1.3 V (see Note B) (cid:1)0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9862701QCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9862701QC A SNJ54AS74AJ 84011012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84011012A SNJ54ALS 74AFK 8401101CA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 8401101CA SNJ54ALS74AJ 8401101DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8401101DA SNJ54ALS74AW JM38510/37101B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37101B2A JM38510/37101BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 37101BCA M38510/37101B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37101B2A M38510/37101BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 37101BCA SN54ALS74AJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54ALS74AJ SN54AS74AJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54AS74AJ SN74ALS74AD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS74A & no Sb/Br) SN74ALS74ADR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS74A & no Sb/Br) SN74ALS74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS74A & no Sb/Br) SN74ALS74AN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74ALS74AN & no Sb/Br) SN74ALS74ANSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS74A & no Sb/Br) SN74AS74AD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS74A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74AS74ADR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS74A & no Sb/Br) SN74AS74AN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74AS74AN & no Sb/Br) SN74AS74ANSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74AS74A & no Sb/Br) SNJ54ALS74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84011012A SNJ54ALS 74AFK SNJ54ALS74AJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 8401101CA SNJ54ALS74AJ SNJ54ALS74AW ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8401101DA SNJ54ALS74AW SNJ54AS74AJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9862701QC A SNJ54AS74AJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A : •Catalog: SN74ALS74A, SN74AS74A •Military: SN54ALS74A, SN54AS74A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ALS74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74AS74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AS74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS74ADR SOIC D 14 2500 367.0 367.0 38.0 SN74ALS74ANSR SO NS 14 2000 367.0 367.0 38.0 SN74AS74ADR SOIC D 14 2500 367.0 367.0 38.0 SN74AS74ANSR SO NS 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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